[Intel-gfx] [PATCH] drm/i915: update VLV PLL and DPIO code v11

[Daniel Vetter]

On Thu, Apr 18, 2013 at 02:51:36PM -0700, Jesse Barnes wrote:
> In Valleyview voltage swing, pre-emphasis and lane control registers can
> be programmed only through the h/w side band fabric.  Update
> vlv_update_pll, i9xx_crtc_enable, and intel_enable_pll with the
> appropriate programming.
> 
> We need to make sure that the tx lane reset occurs in both the full mode
> set and DPMS paths, so factor things out to allow that.
> 
> v2: use different DPIO_DIVISOR values for VGA and DisplayPort
> v3: Fix update pll logic to use same DPIO_DIVISOR & DPIO_REFSFR values
>         for all display interfaces
> v4: collapse with various updates
> v5: squash with crtc enable/pll enable bits
> v6: split out DP code (jbarnes)
>     put phyready check under IS_VALLEYVIEW (jbarnes)
>     remove unneeded check in 9xx pll div update (Jani)
>     wrap VLV pll update call in IS_VALLEYVIEW (Jani)
>     move port enable back to end of crtc enable (jbarnes)
>     put phyready check under IS_VALLEYVIEW (jbarnes)
> v7: fix up conflicts against latest drm-intel-next-queued
> v8: use DPIO reg names, fix pipes (Jani)
>     from mPhy_registers_VLV2_ww20p5 doc
> v9: update to latest info from driver enabling notes doc
>     driver_vbios_notes_9
> v10: fixup a bit of pipe/port confusion to allow eDP and HDMI to work
>      simultaneously (Jesse)
> v11: use pll/port callbacks for DPIO port activity (Daniel)
>      use separate VLV CRTC enable function (Daniel)
>      move around port ready checks (Jesse)
> 
> Signed-off-by: Pallavi G <pallavi.g at intel.com>
> Signed-off-by: Vijay Purushothaman <vijay.a.purushothaman at intel.com>
> Signed-off-by: Gajanan Bhat <gajanan.bhat at intel.com>
> Signed-off-by: Ben Widawsky <benjamin.widawsky at intel.com>
> Signed-off-by: Jesse Barnes <jbarnes at virtuousgeek.org>
Queued for -next, thanks for the patch.
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch