[Intel-gfx] [PATCH 11/17] drm/i915: Add ILK support to intel_read_wm_latency

[Paulo Zanoni]

2013/8/1  <ville.syrjala at linux.intel.com>:
> From: Ville Syrjälä <ville.syrjala at linux.intel.com>
>
> ILK has a slightly different way to read out the watermark
> latency values. On ILK the LP0 latenciy values are in fact
> not stored in any register, and instead we must use fixed
> values.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala at linux.intel.com>

No docs, but seems consistent with the current code.

Reviewed-by: Paulo Zanoni <paulo.r.zanoni at intel.com>

In a follow-up patch you could add an "} else {" statement that prints
a big error message, or even BUG().

> ---
>  drivers/gpu/drm/i915/intel_pm.c | 7 +++++++
>  1 file changed, 7 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index a399ee9..5948f4c 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -2357,6 +2357,13 @@ static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[5])
>                 wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
>                 wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
>                 wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
> +       } else if (INTEL_INFO(dev)->gen >= 5) {
> +               uint32_t mltr = I915_READ(MLTR_ILK);
> +
> +               /* ILK primary LP0 latency is 700 ns */
> +               wm[0] = 7;
> +               wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
> +               wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
>         }
>  }
>
> --
> 1.8.1.5
>
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-- 
Paulo Zanoni