[Intel-gfx] [PATCH v2 13/17] drm/i915: Use the stored cursor and plane latencies properly

[Paulo Zanoni]

2013/8/1  <ville.syrjala at linux.intel.com>:
> From: Ville Syrjälä <ville.syrjala at linux.intel.com>
>
> Rather than pass around the plane latencies, just grab them from
> dev_priv nearer to where they're needed. Do the same for cursor
> latencies.
>
> v2: Add some comments about latency units
>
> Signed-off-by: Ville Syrjälä <ville.syrjala at linux.intel.com>

Reviewed-by: Paulo Zanoni <paulo.r.zanoni at intel.com>

> ---
>  drivers/gpu/drm/i915/intel_pm.c | 34 ++++++++++++++++++++--------------
>  1 file changed, 20 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index afa7f25..f754ca2 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -2255,7 +2255,8 @@ static uint32_t ilk_compute_fbc_wm(struct hsw_pipe_wm_parameters *params,
>                           params->pri_bytes_per_pixel);
>  }
>
> -static bool hsw_compute_lp_wm(uint32_t mem_value, struct hsw_wm_maximums *max,
> +static bool hsw_compute_lp_wm(struct drm_i915_private *dev_priv,
> +                             int level, struct hsw_wm_maximums *max,
>                               struct hsw_pipe_wm_parameters *params,
>                               struct hsw_lp_wm_result *result)
>  {
> @@ -2264,10 +2265,14 @@ static bool hsw_compute_lp_wm(uint32_t mem_value, struct hsw_wm_maximums *max,
>
>         for (pipe = PIPE_A; pipe <= PIPE_C; pipe++) {
>                 struct hsw_pipe_wm_parameters *p = &params[pipe];
> +               /* WM1+ latency values stored in 0.5us units */
> +               uint16_t pri_latency = dev_priv->wm.pri_latency[level] * 5;
> +               uint16_t spr_latency = dev_priv->wm.spr_latency[level] * 5;
> +               uint16_t cur_latency = dev_priv->wm.cur_latency[level] * 5;
>
> -               pri_val[pipe] = ilk_compute_pri_wm(p, mem_value, true);
> -               spr_val[pipe] = ilk_compute_spr_wm(p, mem_value);
> -               cur_val[pipe] = ilk_compute_cur_wm(p, mem_value);
> +               pri_val[pipe] = ilk_compute_pri_wm(p, pri_latency, true);
> +               spr_val[pipe] = ilk_compute_spr_wm(p, spr_latency);
> +               cur_val[pipe] = ilk_compute_cur_wm(p, cur_latency);
>                 fbc_val[pipe] = ilk_compute_fbc_wm(p, pri_val[pipe]);
>         }
>
> @@ -2290,14 +2295,18 @@ static bool hsw_compute_lp_wm(uint32_t mem_value, struct hsw_wm_maximums *max,
>  }
>
>  static uint32_t hsw_compute_wm_pipe(struct drm_i915_private *dev_priv,
> -                                   uint32_t mem_value, enum pipe pipe,
> +                                   enum pipe pipe,
>                                     struct hsw_pipe_wm_parameters *params)
>  {
>         uint32_t pri_val, cur_val, spr_val;
> +       /* WM0 latency values stored in 0.1us units */
> +       uint16_t pri_latency = dev_priv->wm.pri_latency[0];
> +       uint16_t spr_latency = dev_priv->wm.spr_latency[0];
> +       uint16_t cur_latency = dev_priv->wm.cur_latency[0];
>
> -       pri_val = ilk_compute_pri_wm(params, mem_value, false);
> -       spr_val = ilk_compute_spr_wm(params, mem_value);
> -       cur_val = ilk_compute_cur_wm(params, mem_value);
> +       pri_val = ilk_compute_pri_wm(params, pri_latency, false);
> +       spr_val = ilk_compute_spr_wm(params, spr_latency);
> +       cur_val = ilk_compute_cur_wm(params, cur_latency);
>
>         WARN(pri_val > 127,
>              "Primary WM error, mode not supported for pipe %c\n",
> @@ -2463,7 +2472,6 @@ static void hsw_compute_wm_parameters(struct drm_device *dev,
>
>  static void hsw_compute_wm_results(struct drm_device *dev,
>                                    struct hsw_pipe_wm_parameters *params,
> -                                  uint16_t *wm,
>                                    struct hsw_wm_maximums *lp_maximums,
>                                    struct hsw_wm_values *results)
>  {
> @@ -2474,7 +2482,8 @@ static void hsw_compute_wm_results(struct drm_device *dev,
>         int level, max_level, wm_lp;
>
>         for (level = 1; level <= 4; level++)
> -               if (!hsw_compute_lp_wm(wm[level] * 5, lp_maximums, params,
> +               if (!hsw_compute_lp_wm(dev_priv, level,
> +                                      lp_maximums, params,
>                                        &lp_results[level - 1]))
>                         break;
>         max_level = level - 1;
> @@ -2506,8 +2515,7 @@ static void hsw_compute_wm_results(struct drm_device *dev,
>         }
>
>         for_each_pipe(pipe)
> -               results->wm_pipe[pipe] = hsw_compute_wm_pipe(dev_priv, wm[0],
> -                                                            pipe,
> +               results->wm_pipe[pipe] = hsw_compute_wm_pipe(dev_priv, pipe,
>                                                              &params[pipe]);
>
>         for_each_pipe(pipe) {
> @@ -2650,11 +2658,9 @@ static void haswell_update_wm(struct drm_device *dev)
>         hsw_compute_wm_parameters(dev, params, &lp_max_1_2, &lp_max_5_6);
>
>         hsw_compute_wm_results(dev, params,
> -                              dev_priv->wm.pri_latency,
>                                &lp_max_1_2, &results_1_2);
>         if (lp_max_1_2.pri != lp_max_5_6.pri) {
>                 hsw_compute_wm_results(dev, params,
> -                                      dev_priv->wm.pri_latency,
>                                        &lp_max_5_6, &results_5_6);
>                 best_results = hsw_find_best_result(&results_1_2, &results_5_6);
>         } else {
> --
> 1.8.1.5
>
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-- 
Paulo Zanoni