[Intel-gfx] [PATCH] CHROMIUM: drm/i915: Work around PPT chipsets wakeup delays

[james.ausmus at intel.com]

From: Stéphane Marchesin <marcheu at chromium.org>

Right after resume, panther point chipsets seem to ignore all
register writes. But if you wait a bit and retry, everything works
fine. I empirically measured that the window where it is flakey lasts
around 25ms, so let's sleep 30ms after turning on the PCH clock.

BUG=chrome-os-partner:20542
TEST=by hand: resume parrot a couple times, everything works as expected

Change-Id: I3281ff8ef5f43f6f73088a47500a557839acbdc0
Reviewed-on: https://gerrit.chromium.org/gerrit/60164
Reviewed-by: Stuart Abercrombie <sabercrombie at chromium.org>
Commit-Queue: Stéphane Marchesin <marcheu at chromium.org>
Tested-by: Stéphane Marchesin <marcheu at chromium.org>
---
 drivers/gpu/drm/i915/intel_display.c | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 7d13b34..c933bfa 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4833,6 +4833,15 @@ static void ironlake_init_pch_refclk(struct drm_device *dev)
 		POSTING_READ(PCH_DREF_CONTROL);
 		udelay(200);
 	}
+
+	/*
+	 * On resume, the PPT PCH doesn't seem to work right away, and
+	 * sometimes ignores register read/writes until it's completely up.
+	 * Waiting 30ms seems to be long enough to avoid this.
+	 */
+	if (dev_priv->pch_id == INTEL_PCH_PPT_DEVICE_ID_TYPE)
+		msleep(30);
+
 }
 
 /* Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O. */
-- 
1.8.3.2