[Intel-gfx] [PATCH] CHROMIUM: drm/i915: set lower RC6_THRESHOLD for HSW

[james.ausmus at intel.com]

From: Sameer Nanda <snanda at chromium.org>

On Sandybridge/Ivybridge platforms, a higher RC6_THRESHOLD is required
for stability reasons. On Haswell, however, this higher setting is
resulting in an additional ~800mW of power consumption in light GPU
usage scenarios such as blinking cursor. Lowering RC6_THRESHOLD to 50000
on Haswell does not seem to cause stability issues.

Therefore, on SNB/IVB keep the higher threshold for stability reasons,
but on HSW use the default 50000 threshold for power saving reasons.

BUG=chrome-os-partner:20744
TEST=1. On SNB (lumpy) and IVB (link) systems, "intel_reg_read 0xa0b8"
command should return 0x1E848.
2. On Haswell systems, "intel_reg_read 0xa0b8" command should return
0xC350.

Change-Id: I2f7d5895b925dcf3ff96a2756e699797bda4104d
Signed-off-by: Sameer Nanda <snanda at chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/61302
Reviewed-by: Stéphane Marchesin <marcheu at chromium.org>
---
 drivers/gpu/drm/i915/intel_pm.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index a701495..56e65f9 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3166,7 +3166,10 @@ static void gen6_enable_rps(struct drm_device *dev)
 
 	I915_WRITE(GEN6_RC_SLEEP, 0);
 	I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
-	I915_WRITE(GEN6_RC6_THRESHOLD, 125000);
+	if (INTEL_INFO(dev)->gen <= 6 || IS_IVYBRIDGE(dev))
+		I915_WRITE(GEN6_RC6_THRESHOLD, 125000);
+	else
+		I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
 	I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
 	I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
 
-- 
1.8.3.2