[Intel-gfx] [PATCH] drm/i915: Adjust available RPS information through sysfs for vlv

[Daniel Vetter]

On Mon, Aug 26, 2013 at 04:18:54PM +0100, Chris Wilson wrote:
> Valleyview has its own render power state implementation with different
> capability knobs - it has no RP0,RP1,RPn but rather RPe.
> 
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=67734
> Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
> Tested-by: kobe.qin at intel.com
> Reviewed-by: Jani Nikula <jani.nikula at intel.com>

Queued for -next, thanks for the patch.
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch