[Intel-gfx] [PATCH 87/90] assembler: Don't use GL types
Damien Lespiau
damien.lespiau at intel.com
Mon Feb 4 16:28:22 CET 2013
sed -i -e 's/GLuint/unsigned/g' -e 's/GLint/int/g' \
-e 's/GLfloat/float/g' -e 's/GLubyte/uint8_t/g' \
-e 's/GLshort/int16_t/g' assembler/*.[ch]
Drop the GL types here, they don't bring anything to the table. For
instance, GLuint has no guarantee to be 32 bits, so it does not make too
much sense to use it in structure describing hardware tables and
opcodes.
Of course, some bikeshedding can be applied to use uin32_t instead, I
figured that some of the GLuint are used without size constraints, so
a sed with uint32_t did not seem the right thing to do. On top of that
initial sed, one bothered enough could change the structures with size
constraints to actually use uint32_t.
Signed-off-by: Damien Lespiau <damien.lespiau at intel.com>
---
assembler/brw_disasm.c | 82 ++--
assembler/brw_eu.c | 18 +-
assembler/brw_eu.h | 142 ++--
assembler/brw_eu_emit.c | 148 ++--
assembler/brw_eu_util.c | 24 +-
assembler/brw_structs.h | 1698 +++++++++++++++++++++++------------------------
assembler/gen4asm.h | 8 +-
assembler/gram.y | 8 +-
8 files changed, 1058 insertions(+), 1070 deletions(-)
diff --git a/assembler/brw_disasm.c b/assembler/brw_disasm.c
index 9781f6b..de121e6 100644
--- a/assembler/brw_disasm.c
+++ b/assembler/brw_disasm.c
@@ -428,7 +428,7 @@ static int pad (FILE *f, int c)
}
static int control (FILE *file, const char *name, const char * const ctrl[],
- GLuint id, int *space)
+ unsigned id, int *space)
{
if (!ctrl[id]) {
fprintf (file, "*** invalid %s value %d ",
@@ -456,7 +456,7 @@ static int print_opcode (FILE *file, int id)
return 0;
}
-static int reg (FILE *file, GLuint _reg_file, GLuint _reg_nr)
+static int reg (FILE *file, unsigned _reg_file, unsigned _reg_nr)
{
int err = 0;
@@ -585,7 +585,7 @@ static int dest_3src (FILE *file, struct brw_instruction *inst)
}
static int src_align1_region (FILE *file,
- GLuint _vert_stride, GLuint _width, GLuint _horiz_stride)
+ unsigned _vert_stride, unsigned _width, unsigned _horiz_stride)
{
int err = 0;
string (file, "<");
@@ -598,9 +598,9 @@ static int src_align1_region (FILE *file,
return err;
}
-static int src_da1 (FILE *file, GLuint type, GLuint _reg_file,
- GLuint _vert_stride, GLuint _width, GLuint _horiz_stride,
- GLuint reg_num, GLuint sub_reg_num, GLuint __abs, GLuint _negate)
+static int src_da1 (FILE *file, unsigned type, unsigned _reg_file,
+ unsigned _vert_stride, unsigned _width, unsigned _horiz_stride,
+ unsigned reg_num, unsigned sub_reg_num, unsigned __abs, unsigned _negate)
{
int err = 0;
err |= control (file, "negate", negate, _negate, NULL);
@@ -617,16 +617,16 @@ static int src_da1 (FILE *file, GLuint type, GLuint _reg_file,
}
static int src_ia1 (FILE *file,
- GLuint type,
- GLuint _reg_file,
- GLint _addr_imm,
- GLuint _addr_subreg_nr,
- GLuint _negate,
- GLuint __abs,
- GLuint _addr_mode,
- GLuint _horiz_stride,
- GLuint _width,
- GLuint _vert_stride)
+ unsigned type,
+ unsigned _reg_file,
+ int _addr_imm,
+ unsigned _addr_subreg_nr,
+ unsigned _negate,
+ unsigned __abs,
+ unsigned _addr_mode,
+ unsigned _horiz_stride,
+ unsigned _width,
+ unsigned _vert_stride)
{
int err = 0;
err |= control (file, "negate", negate, _negate, NULL);
@@ -644,17 +644,17 @@ static int src_ia1 (FILE *file,
}
static int src_da16 (FILE *file,
- GLuint _reg_type,
- GLuint _reg_file,
- GLuint _vert_stride,
- GLuint _reg_nr,
- GLuint _subreg_nr,
- GLuint __abs,
- GLuint _negate,
- GLuint swz_x,
- GLuint swz_y,
- GLuint swz_z,
- GLuint swz_w)
+ unsigned _reg_type,
+ unsigned _reg_file,
+ unsigned _vert_stride,
+ unsigned _reg_nr,
+ unsigned _subreg_nr,
+ unsigned __abs,
+ unsigned _negate,
+ unsigned swz_x,
+ unsigned swz_y,
+ unsigned swz_z,
+ unsigned swz_w)
{
int err = 0;
err |= control (file, "negate", negate, _negate, NULL);
@@ -703,10 +703,10 @@ static int src_da16 (FILE *file,
static int src0_3src (FILE *file, struct brw_instruction *inst)
{
int err = 0;
- GLuint swz_x = (inst->bits2.da3src.src0_swizzle >> 0) & 0x3;
- GLuint swz_y = (inst->bits2.da3src.src0_swizzle >> 2) & 0x3;
- GLuint swz_z = (inst->bits2.da3src.src0_swizzle >> 4) & 0x3;
- GLuint swz_w = (inst->bits2.da3src.src0_swizzle >> 6) & 0x3;
+ unsigned swz_x = (inst->bits2.da3src.src0_swizzle >> 0) & 0x3;
+ unsigned swz_y = (inst->bits2.da3src.src0_swizzle >> 2) & 0x3;
+ unsigned swz_z = (inst->bits2.da3src.src0_swizzle >> 4) & 0x3;
+ unsigned swz_w = (inst->bits2.da3src.src0_swizzle >> 6) & 0x3;
err |= control (file, "negate", negate, inst->bits1.da3src.src0_negate, NULL);
err |= control (file, "abs", _abs, inst->bits1.da3src.src0_abs, NULL);
@@ -751,11 +751,11 @@ static int src0_3src (FILE *file, struct brw_instruction *inst)
static int src1_3src (FILE *file, struct brw_instruction *inst)
{
int err = 0;
- GLuint swz_x = (inst->bits2.da3src.src1_swizzle >> 0) & 0x3;
- GLuint swz_y = (inst->bits2.da3src.src1_swizzle >> 2) & 0x3;
- GLuint swz_z = (inst->bits2.da3src.src1_swizzle >> 4) & 0x3;
- GLuint swz_w = (inst->bits2.da3src.src1_swizzle >> 6) & 0x3;
- GLuint src1_subreg_nr = (inst->bits2.da3src.src1_subreg_nr_low |
+ unsigned swz_x = (inst->bits2.da3src.src1_swizzle >> 0) & 0x3;
+ unsigned swz_y = (inst->bits2.da3src.src1_swizzle >> 2) & 0x3;
+ unsigned swz_z = (inst->bits2.da3src.src1_swizzle >> 4) & 0x3;
+ unsigned swz_w = (inst->bits2.da3src.src1_swizzle >> 6) & 0x3;
+ unsigned src1_subreg_nr = (inst->bits2.da3src.src1_subreg_nr_low |
(inst->bits3.da3src.src1_subreg_nr_high << 2));
err |= control (file, "negate", negate, inst->bits1.da3src.src1_negate,
@@ -804,10 +804,10 @@ static int src1_3src (FILE *file, struct brw_instruction *inst)
static int src2_3src (FILE *file, struct brw_instruction *inst)
{
int err = 0;
- GLuint swz_x = (inst->bits3.da3src.src2_swizzle >> 0) & 0x3;
- GLuint swz_y = (inst->bits3.da3src.src2_swizzle >> 2) & 0x3;
- GLuint swz_z = (inst->bits3.da3src.src2_swizzle >> 4) & 0x3;
- GLuint swz_w = (inst->bits3.da3src.src2_swizzle >> 6) & 0x3;
+ unsigned swz_x = (inst->bits3.da3src.src2_swizzle >> 0) & 0x3;
+ unsigned swz_y = (inst->bits3.da3src.src2_swizzle >> 2) & 0x3;
+ unsigned swz_z = (inst->bits3.da3src.src2_swizzle >> 4) & 0x3;
+ unsigned swz_w = (inst->bits3.da3src.src2_swizzle >> 6) & 0x3;
err |= control (file, "negate", negate, inst->bits1.da3src.src2_negate,
NULL);
@@ -851,7 +851,7 @@ static int src2_3src (FILE *file, struct brw_instruction *inst)
return err;
}
-static int imm (FILE *file, GLuint type, struct brw_instruction *inst) {
+static int imm (FILE *file, unsigned type, struct brw_instruction *inst) {
switch (type) {
case BRW_REGISTER_TYPE_UD:
format (file, "0x%08xUD", inst->bits3.ud);
diff --git a/assembler/brw_eu.c b/assembler/brw_eu.c
index a9afc82..d874b79 100644
--- a/assembler/brw_eu.c
+++ b/assembler/brw_eu.c
@@ -65,7 +65,7 @@ brw_swap_cmod(uint32_t cmod)
/* How does predicate control work when execution_size != 8? Do I
* need to test/set for 0xffff when execution_size is 16?
*/
-void brw_set_predicate_control_flag_value( struct brw_compile *p, GLuint value )
+void brw_set_predicate_control_flag_value( struct brw_compile *p, unsigned value )
{
p->current->header.predicate_control = BRW_PREDICATE_NONE;
@@ -81,7 +81,7 @@ void brw_set_predicate_control_flag_value( struct brw_compile *p, GLuint value )
}
}
-void brw_set_predicate_control( struct brw_compile *p, GLuint pc )
+void brw_set_predicate_control( struct brw_compile *p, unsigned pc )
{
p->current->header.predicate_control = pc;
}
@@ -91,7 +91,7 @@ void brw_set_predicate_inverse(struct brw_compile *p, bool predicate_inverse)
p->current->header.predicate_inverse = predicate_inverse;
}
-void brw_set_conditionalmod( struct brw_compile *p, GLuint conditional )
+void brw_set_conditionalmod( struct brw_compile *p, unsigned conditional )
{
p->current->header.destreg__conditionalmod = conditional;
}
@@ -102,7 +102,7 @@ void brw_set_flag_reg(struct brw_compile *p, int reg, int subreg)
p->current->bits2.da1.flag_subreg_nr = subreg;
}
-void brw_set_access_mode( struct brw_compile *p, GLuint access_mode )
+void brw_set_access_mode( struct brw_compile *p, unsigned access_mode )
{
p->current->header.access_mode = access_mode;
}
@@ -144,7 +144,7 @@ brw_set_compression_control(struct brw_compile *p,
}
}
-void brw_set_mask_control( struct brw_compile *p, GLuint value )
+void brw_set_mask_control( struct brw_compile *p, unsigned value )
{
p->current->header.mask_control = value;
}
@@ -154,7 +154,7 @@ void brw_set_saturate( struct brw_compile *p, bool enable )
p->current->header.saturate = enable;
}
-void brw_set_acc_write_control(struct brw_compile *p, GLuint value)
+void brw_set_acc_write_control(struct brw_compile *p, unsigned value)
{
if (p->brw->intel.gen >= 6)
p->current->header.acc_wr_control = value;
@@ -219,13 +219,13 @@ brw_init_compile(struct brw_context *brw, struct brw_compile *p, void *mem_ctx)
}
-const GLuint *brw_get_program( struct brw_compile *p,
- GLuint *sz )
+const unsigned *brw_get_program( struct brw_compile *p,
+ unsigned *sz )
{
brw_compact_instructions(p);
*sz = p->next_insn_offset;
- return (const GLuint *)p->store;
+ return (const unsigned *)p->store;
}
void
diff --git a/assembler/brw_eu.h b/assembler/brw_eu.h
index 83c82d1..427db37 100644
--- a/assembler/brw_eu.h
+++ b/assembler/brw_eu.h
@@ -49,7 +49,7 @@ extern "C" {
struct brw_compile {
struct brw_instruction *store;
int store_size;
- GLuint nr_insn;
+ unsigned nr_insn;
unsigned int next_insn_offset;
void *mem_ctx;
@@ -60,7 +60,7 @@ struct brw_compile {
bool compressed_stack[BRW_EU_MAX_INSN_STACK];
struct brw_instruction *current;
- GLuint flag_value;
+ unsigned flag_value;
bool single_program_flow;
bool compressed;
struct brw_context *brw;
@@ -98,23 +98,23 @@ static inline struct brw_instruction *current_insn( struct brw_compile *p)
void brw_pop_insn_state( struct brw_compile *p );
void brw_push_insn_state( struct brw_compile *p );
-void brw_set_mask_control( struct brw_compile *p, GLuint value );
+void brw_set_mask_control( struct brw_compile *p, unsigned value );
void brw_set_saturate( struct brw_compile *p, bool enable );
-void brw_set_access_mode( struct brw_compile *p, GLuint access_mode );
+void brw_set_access_mode( struct brw_compile *p, unsigned access_mode );
void brw_set_compression_control(struct brw_compile *p, enum brw_compression c);
-void brw_set_predicate_control_flag_value( struct brw_compile *p, GLuint value );
-void brw_set_predicate_control( struct brw_compile *p, GLuint pc );
+void brw_set_predicate_control_flag_value( struct brw_compile *p, unsigned value );
+void brw_set_predicate_control( struct brw_compile *p, unsigned pc );
void brw_set_predicate_inverse(struct brw_compile *p, bool predicate_inverse);
-void brw_set_conditionalmod( struct brw_compile *p, GLuint conditional );
+void brw_set_conditionalmod( struct brw_compile *p, unsigned conditional );
void brw_set_flag_reg(struct brw_compile *p, int reg, int subreg);
-void brw_set_acc_write_control(struct brw_compile *p, GLuint value);
+void brw_set_acc_write_control(struct brw_compile *p, unsigned value);
void brw_init_compile(struct brw_context *, struct brw_compile *p,
void *mem_ctx);
void brw_dump_compile(struct brw_compile *p, FILE *out, int start, int end);
-const GLuint *brw_get_program( struct brw_compile *p, GLuint *sz );
+const unsigned *brw_get_program( struct brw_compile *p, unsigned *sz );
-struct brw_instruction *brw_next_insn(struct brw_compile *p, GLuint opcode);
+struct brw_instruction *brw_next_insn(struct brw_compile *p, unsigned opcode);
void brw_set_dest(struct brw_compile *p, struct brw_instruction *insn,
struct brw_reg dest);
void brw_set_src0(struct brw_compile *p, struct brw_instruction *insn,
@@ -122,7 +122,7 @@ void brw_set_src0(struct brw_compile *p, struct brw_instruction *insn,
void gen6_resolve_implied_move(struct brw_compile *p,
struct brw_reg *src,
- GLuint msg_reg_nr);
+ unsigned msg_reg_nr);
/* Helpers for regular instructions:
*/
@@ -188,101 +188,101 @@ ROUND(RNDE)
*/
void brw_set_sampler_message(struct brw_compile *p,
struct brw_instruction *insn,
- GLuint binding_table_index,
- GLuint sampler,
- GLuint msg_type,
- GLuint response_length,
- GLuint msg_length,
- GLuint header_present,
- GLuint simd_mode,
- GLuint return_format);
+ unsigned binding_table_index,
+ unsigned sampler,
+ unsigned msg_type,
+ unsigned response_length,
+ unsigned msg_length,
+ unsigned header_present,
+ unsigned simd_mode,
+ unsigned return_format);
void brw_set_dp_read_message(struct brw_compile *p,
struct brw_instruction *insn,
- GLuint binding_table_index,
- GLuint msg_control,
- GLuint msg_type,
- GLuint target_cache,
- GLuint msg_length,
+ unsigned binding_table_index,
+ unsigned msg_control,
+ unsigned msg_type,
+ unsigned target_cache,
+ unsigned msg_length,
bool header_present,
- GLuint response_length);
+ unsigned response_length);
void brw_set_dp_write_message(struct brw_compile *p,
struct brw_instruction *insn,
- GLuint binding_table_index,
- GLuint msg_control,
- GLuint msg_type,
- GLuint msg_length,
+ unsigned binding_table_index,
+ unsigned msg_control,
+ unsigned msg_type,
+ unsigned msg_length,
bool header_present,
- GLuint last_render_target,
- GLuint response_length,
- GLuint end_of_thread,
- GLuint send_commit_msg);
+ unsigned last_render_target,
+ unsigned response_length,
+ unsigned end_of_thread,
+ unsigned send_commit_msg);
void brw_urb_WRITE(struct brw_compile *p,
struct brw_reg dest,
- GLuint msg_reg_nr,
+ unsigned msg_reg_nr,
struct brw_reg src0,
bool allocate,
bool used,
- GLuint msg_length,
- GLuint response_length,
+ unsigned msg_length,
+ unsigned response_length,
bool eot,
bool writes_complete,
- GLuint offset,
- GLuint swizzle);
+ unsigned offset,
+ unsigned swizzle);
void brw_ff_sync(struct brw_compile *p,
struct brw_reg dest,
- GLuint msg_reg_nr,
+ unsigned msg_reg_nr,
struct brw_reg src0,
bool allocate,
- GLuint response_length,
+ unsigned response_length,
bool eot);
void brw_svb_write(struct brw_compile *p,
struct brw_reg dest,
- GLuint msg_reg_nr,
+ unsigned msg_reg_nr,
struct brw_reg src0,
- GLuint binding_table_index,
+ unsigned binding_table_index,
bool send_commit_msg);
void brw_fb_WRITE(struct brw_compile *p,
int dispatch_width,
- GLuint msg_reg_nr,
+ unsigned msg_reg_nr,
struct brw_reg src0,
- GLuint msg_control,
- GLuint binding_table_index,
- GLuint msg_length,
- GLuint response_length,
+ unsigned msg_control,
+ unsigned binding_table_index,
+ unsigned msg_length,
+ unsigned response_length,
bool eot,
bool header_present);
void brw_SAMPLE(struct brw_compile *p,
struct brw_reg dest,
- GLuint msg_reg_nr,
+ unsigned msg_reg_nr,
struct brw_reg src0,
- GLuint binding_table_index,
- GLuint sampler,
- GLuint writemask,
- GLuint msg_type,
- GLuint response_length,
- GLuint msg_length,
- GLuint header_present,
- GLuint simd_mode,
- GLuint return_format);
+ unsigned binding_table_index,
+ unsigned sampler,
+ unsigned writemask,
+ unsigned msg_type,
+ unsigned response_length,
+ unsigned msg_length,
+ unsigned header_present,
+ unsigned simd_mode,
+ unsigned return_format);
void brw_math( struct brw_compile *p,
struct brw_reg dest,
- GLuint function,
- GLuint msg_reg_nr,
+ unsigned function,
+ unsigned msg_reg_nr,
struct brw_reg src,
- GLuint data_type,
- GLuint precision );
+ unsigned data_type,
+ unsigned precision );
void brw_math2(struct brw_compile *p,
struct brw_reg dest,
- GLuint function,
+ unsigned function,
struct brw_reg src0,
struct brw_reg src1);
@@ -296,12 +296,12 @@ void brw_oword_block_read_scratch(struct brw_compile *p,
struct brw_reg dest,
struct brw_reg mrf,
int num_regs,
- GLuint offset);
+ unsigned offset);
void brw_oword_block_write_scratch(struct brw_compile *p,
struct brw_reg mrf,
int num_regs,
- GLuint offset);
+ unsigned offset);
void brw_shader_time_add(struct brw_compile *p,
int mrf,
@@ -311,7 +311,7 @@ void brw_shader_time_add(struct brw_compile *p,
* channel.
*/
struct brw_instruction *brw_IF(struct brw_compile *p,
- GLuint execute_size);
+ unsigned execute_size);
struct brw_instruction *gen6_IF(struct brw_compile *p, uint32_t conditional,
struct brw_reg src0, struct brw_reg src1);
@@ -321,7 +321,7 @@ void brw_ENDIF(struct brw_compile *p);
/* DO/WHILE loops:
*/
struct brw_instruction *brw_DO(struct brw_compile *p,
- GLuint execute_size);
+ unsigned execute_size);
struct brw_instruction *brw_WHILE(struct brw_compile *p);
@@ -344,7 +344,7 @@ void brw_WAIT(struct brw_compile *p);
*/
void brw_CMP(struct brw_compile *p,
struct brw_reg dest,
- GLuint conditional,
+ unsigned conditional,
struct brw_reg src0,
struct brw_reg src1);
@@ -355,22 +355,22 @@ void brw_CMP(struct brw_compile *p,
void brw_copy_indirect_to_indirect(struct brw_compile *p,
struct brw_indirect dst_ptr,
struct brw_indirect src_ptr,
- GLuint count);
+ unsigned count);
void brw_copy_from_indirect(struct brw_compile *p,
struct brw_reg dst,
struct brw_indirect ptr,
- GLuint count);
+ unsigned count);
void brw_copy4(struct brw_compile *p,
struct brw_reg dst,
struct brw_reg src,
- GLuint count);
+ unsigned count);
void brw_copy8(struct brw_compile *p,
struct brw_reg dst,
struct brw_reg src,
- GLuint count);
+ unsigned count);
void brw_math_invert( struct brw_compile *p,
struct brw_reg dst,
diff --git a/assembler/brw_eu_emit.c b/assembler/brw_eu_emit.c
index a1e96d1..23f0da5 100644
--- a/assembler/brw_eu_emit.c
+++ b/assembler/brw_eu_emit.c
@@ -62,7 +62,7 @@ static void guess_execution_size(struct brw_compile *p,
void
gen6_resolve_implied_move(struct brw_compile *p,
struct brw_reg *src,
- GLuint msg_reg_nr)
+ unsigned msg_reg_nr)
{
struct intel_context *intel = &p->brw->intel;
if (intel->gen < 6)
@@ -478,10 +478,10 @@ brw_set_message_descriptor(struct brw_compile *p,
static void brw_set_math_message( struct brw_compile *p,
struct brw_instruction *insn,
- GLuint function,
- GLuint integer_type,
+ unsigned function,
+ unsigned integer_type,
bool low_precision,
- GLuint dataType )
+ unsigned dataType )
{
struct brw_context *brw = p->brw;
struct intel_context *intel = &brw->intel;
@@ -536,7 +536,7 @@ static void brw_set_math_message( struct brw_compile *p,
static void brw_set_ff_sync_message(struct brw_compile *p,
struct brw_instruction *insn,
bool allocate,
- GLuint response_length,
+ unsigned response_length,
bool end_of_thread)
{
brw_set_message_descriptor(p, insn, BRW_SFID_URB,
@@ -553,12 +553,12 @@ static void brw_set_urb_message( struct brw_compile *p,
struct brw_instruction *insn,
bool allocate,
bool used,
- GLuint msg_length,
- GLuint response_length,
+ unsigned msg_length,
+ unsigned response_length,
bool end_of_thread,
bool complete,
- GLuint offset,
- GLuint swizzle_control )
+ unsigned offset,
+ unsigned swizzle_control )
{
struct brw_context *brw = p->brw;
struct intel_context *intel = &brw->intel;
@@ -593,15 +593,15 @@ static void brw_set_urb_message( struct brw_compile *p,
void
brw_set_dp_write_message(struct brw_compile *p,
struct brw_instruction *insn,
- GLuint binding_table_index,
- GLuint msg_control,
- GLuint msg_type,
- GLuint msg_length,
+ unsigned binding_table_index,
+ unsigned msg_control,
+ unsigned msg_type,
+ unsigned msg_length,
bool header_present,
- GLuint last_render_target,
- GLuint response_length,
- GLuint end_of_thread,
- GLuint send_commit_msg)
+ unsigned last_render_target,
+ unsigned response_length,
+ unsigned end_of_thread,
+ unsigned send_commit_msg)
{
struct brw_context *brw = p->brw;
struct intel_context *intel = &brw->intel;
@@ -652,13 +652,13 @@ brw_set_dp_write_message(struct brw_compile *p,
void
brw_set_dp_read_message(struct brw_compile *p,
struct brw_instruction *insn,
- GLuint binding_table_index,
- GLuint msg_control,
- GLuint msg_type,
- GLuint target_cache,
- GLuint msg_length,
+ unsigned binding_table_index,
+ unsigned msg_control,
+ unsigned msg_type,
+ unsigned target_cache,
+ unsigned msg_length,
bool header_present,
- GLuint response_length)
+ unsigned response_length)
{
struct brw_context *brw = p->brw;
struct intel_context *intel = &brw->intel;
@@ -708,14 +708,14 @@ brw_set_dp_read_message(struct brw_compile *p,
void
brw_set_sampler_message(struct brw_compile *p,
struct brw_instruction *insn,
- GLuint binding_table_index,
- GLuint sampler,
- GLuint msg_type,
- GLuint response_length,
- GLuint msg_length,
- GLuint header_present,
- GLuint simd_mode,
- GLuint return_format)
+ unsigned binding_table_index,
+ unsigned sampler,
+ unsigned msg_type,
+ unsigned response_length,
+ unsigned msg_length,
+ unsigned header_present,
+ unsigned simd_mode,
+ unsigned return_format)
{
struct brw_context *brw = p->brw;
struct intel_context *intel = &brw->intel;
@@ -748,7 +748,7 @@ brw_set_sampler_message(struct brw_compile *p,
#define next_insn brw_next_insn
struct brw_instruction *
-brw_next_insn(struct brw_compile *p, GLuint opcode)
+brw_next_insn(struct brw_compile *p, unsigned opcode)
{
struct brw_instruction *insn;
@@ -779,7 +779,7 @@ brw_next_insn(struct brw_compile *p, GLuint opcode)
}
static struct brw_instruction *brw_alu1( struct brw_compile *p,
- GLuint opcode,
+ unsigned opcode,
struct brw_reg dest,
struct brw_reg src )
{
@@ -790,7 +790,7 @@ static struct brw_instruction *brw_alu1( struct brw_compile *p,
}
static struct brw_instruction *brw_alu2(struct brw_compile *p,
- GLuint opcode,
+ unsigned opcode,
struct brw_reg dest,
struct brw_reg src0,
struct brw_reg src1 )
@@ -902,7 +902,7 @@ brw_set_3src_src2(struct brw_compile *p,
}
static struct brw_instruction *brw_alu3(struct brw_compile *p,
- GLuint opcode,
+ unsigned opcode,
struct brw_reg dest,
struct brw_reg src0,
struct brw_reg src1,
@@ -1170,7 +1170,7 @@ get_inner_do_insn(struct brw_compile *p)
* popped off. If the stack is now empty, normal execution resumes.
*/
struct brw_instruction *
-brw_IF(struct brw_compile *p, GLuint execute_size)
+brw_IF(struct brw_compile *p, unsigned execute_size)
{
struct intel_context *intel = &p->brw->intel;
struct brw_instruction *insn;
@@ -1572,7 +1572,7 @@ struct brw_instruction *gen6_HALT(struct brw_compile *p)
* For gen6, there's no more mask stack, so no need for DO. WHILE
* just points back to the first instruction of the loop.
*/
-struct brw_instruction *brw_DO(struct brw_compile *p, GLuint execute_size)
+struct brw_instruction *brw_DO(struct brw_compile *p, unsigned execute_size)
{
struct intel_context *intel = &p->brw->intel;
@@ -1634,7 +1634,7 @@ struct brw_instruction *brw_WHILE(struct brw_compile *p)
{
struct intel_context *intel = &p->brw->intel;
struct brw_instruction *insn, *do_insn;
- GLuint br = 1;
+ unsigned br = 1;
if (intel->gen >= 5)
br = 2;
@@ -1701,7 +1701,7 @@ void brw_land_fwd_jump(struct brw_compile *p, int jmp_insn_idx)
{
struct intel_context *intel = &p->brw->intel;
struct brw_instruction *jmp_insn = &p->store[jmp_insn_idx];
- GLuint jmpi = 1;
+ unsigned jmpi = 1;
if (intel->gen >= 5)
jmpi = 2;
@@ -1720,7 +1720,7 @@ void brw_land_fwd_jump(struct brw_compile *p, int jmp_insn_idx)
*/
void brw_CMP(struct brw_compile *p,
struct brw_reg dest,
- GLuint conditional,
+ unsigned conditional,
struct brw_reg src0,
struct brw_reg src1)
{
@@ -1769,11 +1769,11 @@ void brw_WAIT (struct brw_compile *p)
*/
void brw_math( struct brw_compile *p,
struct brw_reg dest,
- GLuint function,
- GLuint msg_reg_nr,
+ unsigned function,
+ unsigned msg_reg_nr,
struct brw_reg src,
- GLuint data_type,
- GLuint precision )
+ unsigned data_type,
+ unsigned precision )
{
struct intel_context *intel = &p->brw->intel;
@@ -1833,7 +1833,7 @@ void brw_math( struct brw_compile *p,
*/
void brw_math2(struct brw_compile *p,
struct brw_reg dest,
- GLuint function,
+ unsigned function,
struct brw_reg src0,
struct brw_reg src1)
{
@@ -1893,7 +1893,7 @@ void brw_math2(struct brw_compile *p,
void brw_oword_block_write_scratch(struct brw_compile *p,
struct brw_reg mrf,
int num_regs,
- GLuint offset)
+ unsigned offset)
{
struct intel_context *intel = &p->brw->intel;
uint32_t msg_control, msg_type;
@@ -2005,7 +2005,7 @@ brw_oword_block_read_scratch(struct brw_compile *p,
struct brw_reg dest,
struct brw_reg mrf,
int num_regs,
- GLuint offset)
+ unsigned offset)
{
struct intel_context *intel = &p->brw->intel;
uint32_t msg_control;
@@ -2130,18 +2130,18 @@ void brw_oword_block_read(struct brw_compile *p,
void brw_fb_WRITE(struct brw_compile *p,
int dispatch_width,
- GLuint msg_reg_nr,
+ unsigned msg_reg_nr,
struct brw_reg src0,
- GLuint msg_control,
- GLuint binding_table_index,
- GLuint msg_length,
- GLuint response_length,
+ unsigned msg_control,
+ unsigned binding_table_index,
+ unsigned msg_length,
+ unsigned response_length,
bool eot,
bool header_present)
{
struct intel_context *intel = &p->brw->intel;
struct brw_instruction *insn;
- GLuint msg_type;
+ unsigned msg_type;
struct brw_reg dest;
if (dispatch_width == 16)
@@ -2192,17 +2192,17 @@ void brw_fb_WRITE(struct brw_compile *p,
*/
void brw_SAMPLE(struct brw_compile *p,
struct brw_reg dest,
- GLuint msg_reg_nr,
+ unsigned msg_reg_nr,
struct brw_reg src0,
- GLuint binding_table_index,
- GLuint sampler,
- GLuint writemask,
- GLuint msg_type,
- GLuint response_length,
- GLuint msg_length,
- GLuint header_present,
- GLuint simd_mode,
- GLuint return_format)
+ unsigned binding_table_index,
+ unsigned sampler,
+ unsigned writemask,
+ unsigned msg_type,
+ unsigned response_length,
+ unsigned msg_length,
+ unsigned header_present,
+ unsigned simd_mode,
+ unsigned return_format)
{
struct intel_context *intel = &p->brw->intel;
bool need_stall = 0;
@@ -2223,8 +2223,8 @@ void brw_SAMPLE(struct brw_compile *p,
* needed.
*/
if (writemask != BRW_WRITEMASK_XYZW) {
- GLuint dst_offset = 0;
- GLuint i, newmask = 0, len = 0;
+ unsigned dst_offset = 0;
+ unsigned i, newmask = 0, len = 0;
for (i = 0; i < 4; i++) {
if (writemask & (1<<i))
@@ -2320,16 +2320,16 @@ void brw_SAMPLE(struct brw_compile *p,
*/
void brw_urb_WRITE(struct brw_compile *p,
struct brw_reg dest,
- GLuint msg_reg_nr,
+ unsigned msg_reg_nr,
struct brw_reg src0,
bool allocate,
bool used,
- GLuint msg_length,
- GLuint response_length,
+ unsigned msg_length,
+ unsigned response_length,
bool eot,
bool writes_complete,
- GLuint offset,
- GLuint swizzle)
+ unsigned offset,
+ unsigned swizzle)
{
struct intel_context *intel = &p->brw->intel;
struct brw_instruction *insn;
@@ -2509,10 +2509,10 @@ brw_set_uip_jip(struct brw_compile *p)
void brw_ff_sync(struct brw_compile *p,
struct brw_reg dest,
- GLuint msg_reg_nr,
+ unsigned msg_reg_nr,
struct brw_reg src0,
bool allocate,
- GLuint response_length,
+ unsigned response_length,
bool eot)
{
struct intel_context *intel = &p->brw->intel;
@@ -2549,9 +2549,9 @@ void brw_ff_sync(struct brw_compile *p,
void
brw_svb_write(struct brw_compile *p,
struct brw_reg dest,
- GLuint msg_reg_nr,
+ unsigned msg_reg_nr,
struct brw_reg src0,
- GLuint binding_table_index,
+ unsigned binding_table_index,
bool send_commit_msg)
{
struct brw_instruction *insn;
diff --git a/assembler/brw_eu_util.c b/assembler/brw_eu_util.c
index e3bfbc7..f9126ab 100644
--- a/assembler/brw_eu_util.c
+++ b/assembler/brw_eu_util.c
@@ -53,16 +53,16 @@ void brw_math_invert( struct brw_compile *p,
void brw_copy4(struct brw_compile *p,
struct brw_reg dst,
struct brw_reg src,
- GLuint count)
+ unsigned count)
{
- GLuint i;
+ unsigned i;
dst = vec4(dst);
src = vec4(src);
for (i = 0; i < count; i++)
{
- GLuint delta = i*32;
+ unsigned delta = i*32;
brw_MOV(p, byte_offset(dst, delta), byte_offset(src, delta));
brw_MOV(p, byte_offset(dst, delta+16), byte_offset(src, delta+16));
}
@@ -72,16 +72,16 @@ void brw_copy4(struct brw_compile *p,
void brw_copy8(struct brw_compile *p,
struct brw_reg dst,
struct brw_reg src,
- GLuint count)
+ unsigned count)
{
- GLuint i;
+ unsigned i;
dst = vec8(dst);
src = vec8(src);
for (i = 0; i < count; i++)
{
- GLuint delta = i*32;
+ unsigned delta = i*32;
brw_MOV(p, byte_offset(dst, delta), byte_offset(src, delta));
}
}
@@ -90,13 +90,13 @@ void brw_copy8(struct brw_compile *p,
void brw_copy_indirect_to_indirect(struct brw_compile *p,
struct brw_indirect dst_ptr,
struct brw_indirect src_ptr,
- GLuint count)
+ unsigned count)
{
- GLuint i;
+ unsigned i;
for (i = 0; i < count; i++)
{
- GLuint delta = i*32;
+ unsigned delta = i*32;
brw_MOV(p, deref_4f(dst_ptr, delta), deref_4f(src_ptr, delta));
brw_MOV(p, deref_4f(dst_ptr, delta+16), deref_4f(src_ptr, delta+16));
}
@@ -106,15 +106,15 @@ void brw_copy_indirect_to_indirect(struct brw_compile *p,
void brw_copy_from_indirect(struct brw_compile *p,
struct brw_reg dst,
struct brw_indirect ptr,
- GLuint count)
+ unsigned count)
{
- GLuint i;
+ unsigned i;
dst = vec4(dst);
for (i = 0; i < count; i++)
{
- GLuint delta = i*32;
+ unsigned delta = i*32;
brw_MOV(p, byte_offset(dst, delta), deref_4f(ptr, delta));
brw_MOV(p, byte_offset(dst, delta+16), deref_4f(ptr, delta+16));
}
diff --git a/assembler/brw_structs.h b/assembler/brw_structs.h
index 2f6aafb..8c2d2b9 100644
--- a/assembler/brw_structs.h
+++ b/assembler/brw_structs.h
@@ -35,12 +35,6 @@
#include <stdint.h>
-typedef unsigned char GLubyte;
-typedef short GLshort;
-typedef unsigned int GLuint;
-typedef int GLint;
-typedef float GLfloat;
-
/* These seem to be passed around as function args, so it works out
* better to keep them as #defines:
*/
@@ -53,31 +47,31 @@ struct brw_urb_fence
{
struct
{
- GLuint length:8;
- GLuint vs_realloc:1;
- GLuint gs_realloc:1;
- GLuint clp_realloc:1;
- GLuint sf_realloc:1;
- GLuint vfe_realloc:1;
- GLuint cs_realloc:1;
- GLuint pad:2;
- GLuint opcode:16;
+ unsigned length:8;
+ unsigned vs_realloc:1;
+ unsigned gs_realloc:1;
+ unsigned clp_realloc:1;
+ unsigned sf_realloc:1;
+ unsigned vfe_realloc:1;
+ unsigned cs_realloc:1;
+ unsigned pad:2;
+ unsigned opcode:16;
} header;
struct
{
- GLuint vs_fence:10;
- GLuint gs_fence:10;
- GLuint clp_fence:10;
- GLuint pad:2;
+ unsigned vs_fence:10;
+ unsigned gs_fence:10;
+ unsigned clp_fence:10;
+ unsigned pad:2;
} bits0;
struct
{
- GLuint sf_fence:10;
- GLuint vf_fence:10;
- GLuint cs_fence:11;
- GLuint pad:1;
+ unsigned sf_fence:10;
+ unsigned vf_fence:10;
+ unsigned cs_fence:11;
+ unsigned pad:1;
} bits1;
};
@@ -87,48 +81,48 @@ struct brw_urb_fence
struct thread0
{
- GLuint pad0:1;
- GLuint grf_reg_count:3;
- GLuint pad1:2;
- GLuint kernel_start_pointer:26; /* Offset from GENERAL_STATE_BASE */
+ unsigned pad0:1;
+ unsigned grf_reg_count:3;
+ unsigned pad1:2;
+ unsigned kernel_start_pointer:26; /* Offset from GENERAL_STATE_BASE */
};
struct thread1
{
- GLuint ext_halt_exception_enable:1;
- GLuint sw_exception_enable:1;
- GLuint mask_stack_exception_enable:1;
- GLuint timeout_exception_enable:1;
- GLuint illegal_op_exception_enable:1;
- GLuint pad0:3;
- GLuint depth_coef_urb_read_offset:6; /* WM only */
- GLuint pad1:2;
- GLuint floating_point_mode:1;
- GLuint thread_priority:1;
- GLuint binding_table_entry_count:8;
- GLuint pad3:5;
- GLuint single_program_flow:1;
+ unsigned ext_halt_exception_enable:1;
+ unsigned sw_exception_enable:1;
+ unsigned mask_stack_exception_enable:1;
+ unsigned timeout_exception_enable:1;
+ unsigned illegal_op_exception_enable:1;
+ unsigned pad0:3;
+ unsigned depth_coef_urb_read_offset:6; /* WM only */
+ unsigned pad1:2;
+ unsigned floating_point_mode:1;
+ unsigned thread_priority:1;
+ unsigned binding_table_entry_count:8;
+ unsigned pad3:5;
+ unsigned single_program_flow:1;
};
struct thread2
{
- GLuint per_thread_scratch_space:4;
- GLuint pad0:6;
- GLuint scratch_space_base_pointer:22;
+ unsigned per_thread_scratch_space:4;
+ unsigned pad0:6;
+ unsigned scratch_space_base_pointer:22;
};
struct thread3
{
- GLuint dispatch_grf_start_reg:4;
- GLuint urb_entry_read_offset:6;
- GLuint pad0:1;
- GLuint urb_entry_read_length:6;
- GLuint pad1:1;
- GLuint const_urb_entry_read_offset:6;
- GLuint pad2:1;
- GLuint const_urb_entry_read_length:6;
- GLuint pad3:1;
+ unsigned dispatch_grf_start_reg:4;
+ unsigned urb_entry_read_offset:6;
+ unsigned pad0:1;
+ unsigned urb_entry_read_length:6;
+ unsigned pad1:1;
+ unsigned const_urb_entry_read_offset:6;
+ unsigned pad2:1;
+ unsigned const_urb_entry_read_length:6;
+ unsigned pad3:1;
};
@@ -138,18 +132,18 @@ struct brw_clip_unit_state
struct thread0 thread0;
struct
{
- GLuint pad0:7;
- GLuint sw_exception_enable:1;
- GLuint pad1:3;
- GLuint mask_stack_exception_enable:1;
- GLuint pad2:1;
- GLuint illegal_op_exception_enable:1;
- GLuint pad3:2;
- GLuint floating_point_mode:1;
- GLuint thread_priority:1;
- GLuint binding_table_entry_count:8;
- GLuint pad4:5;
- GLuint single_program_flow:1;
+ unsigned pad0:7;
+ unsigned sw_exception_enable:1;
+ unsigned pad1:3;
+ unsigned mask_stack_exception_enable:1;
+ unsigned pad2:1;
+ unsigned illegal_op_exception_enable:1;
+ unsigned pad3:2;
+ unsigned floating_point_mode:1;
+ unsigned thread_priority:1;
+ unsigned binding_table_entry_count:8;
+ unsigned pad4:5;
+ unsigned single_program_flow:1;
} thread1;
struct thread2 thread2;
@@ -157,142 +151,142 @@ struct brw_clip_unit_state
struct
{
- GLuint pad0:9;
- GLuint gs_output_stats:1; /* not always */
- GLuint stats_enable:1;
- GLuint nr_urb_entries:7;
- GLuint pad1:1;
- GLuint urb_entry_allocation_size:5;
- GLuint pad2:1;
- GLuint max_threads:5; /* may be less */
- GLuint pad3:2;
+ unsigned pad0:9;
+ unsigned gs_output_stats:1; /* not always */
+ unsigned stats_enable:1;
+ unsigned nr_urb_entries:7;
+ unsigned pad1:1;
+ unsigned urb_entry_allocation_size:5;
+ unsigned pad2:1;
+ unsigned max_threads:5; /* may be less */
+ unsigned pad3:2;
} thread4;
struct
{
- GLuint pad0:13;
- GLuint clip_mode:3;
- GLuint userclip_enable_flags:8;
- GLuint userclip_must_clip:1;
- GLuint negative_w_clip_test:1;
- GLuint guard_band_enable:1;
- GLuint viewport_z_clip_enable:1;
- GLuint viewport_xy_clip_enable:1;
- GLuint vertex_position_space:1;
- GLuint api_mode:1;
- GLuint pad2:1;
+ unsigned pad0:13;
+ unsigned clip_mode:3;
+ unsigned userclip_enable_flags:8;
+ unsigned userclip_must_clip:1;
+ unsigned negative_w_clip_test:1;
+ unsigned guard_band_enable:1;
+ unsigned viewport_z_clip_enable:1;
+ unsigned viewport_xy_clip_enable:1;
+ unsigned vertex_position_space:1;
+ unsigned api_mode:1;
+ unsigned pad2:1;
} clip5;
struct
{
- GLuint pad0:5;
- GLuint clipper_viewport_state_ptr:27;
+ unsigned pad0:5;
+ unsigned clipper_viewport_state_ptr:27;
} clip6;
- GLfloat viewport_xmin;
- GLfloat viewport_xmax;
- GLfloat viewport_ymin;
- GLfloat viewport_ymax;
+ float viewport_xmin;
+ float viewport_xmax;
+ float viewport_ymin;
+ float viewport_ymax;
};
struct gen6_blend_state
{
struct {
- GLuint dest_blend_factor:5;
- GLuint source_blend_factor:5;
- GLuint pad3:1;
- GLuint blend_func:3;
- GLuint pad2:1;
- GLuint ia_dest_blend_factor:5;
- GLuint ia_source_blend_factor:5;
- GLuint pad1:1;
- GLuint ia_blend_func:3;
- GLuint pad0:1;
- GLuint ia_blend_enable:1;
- GLuint blend_enable:1;
+ unsigned dest_blend_factor:5;
+ unsigned source_blend_factor:5;
+ unsigned pad3:1;
+ unsigned blend_func:3;
+ unsigned pad2:1;
+ unsigned ia_dest_blend_factor:5;
+ unsigned ia_source_blend_factor:5;
+ unsigned pad1:1;
+ unsigned ia_blend_func:3;
+ unsigned pad0:1;
+ unsigned ia_blend_enable:1;
+ unsigned blend_enable:1;
} blend0;
struct {
- GLuint post_blend_clamp_enable:1;
- GLuint pre_blend_clamp_enable:1;
- GLuint clamp_range:2;
- GLuint pad0:4;
- GLuint x_dither_offset:2;
- GLuint y_dither_offset:2;
- GLuint dither_enable:1;
- GLuint alpha_test_func:3;
- GLuint alpha_test_enable:1;
- GLuint pad1:1;
- GLuint logic_op_func:4;
- GLuint logic_op_enable:1;
- GLuint pad2:1;
- GLuint write_disable_b:1;
- GLuint write_disable_g:1;
- GLuint write_disable_r:1;
- GLuint write_disable_a:1;
- GLuint pad3:1;
- GLuint alpha_to_coverage_dither:1;
- GLuint alpha_to_one:1;
- GLuint alpha_to_coverage:1;
+ unsigned post_blend_clamp_enable:1;
+ unsigned pre_blend_clamp_enable:1;
+ unsigned clamp_range:2;
+ unsigned pad0:4;
+ unsigned x_dither_offset:2;
+ unsigned y_dither_offset:2;
+ unsigned dither_enable:1;
+ unsigned alpha_test_func:3;
+ unsigned alpha_test_enable:1;
+ unsigned pad1:1;
+ unsigned logic_op_func:4;
+ unsigned logic_op_enable:1;
+ unsigned pad2:1;
+ unsigned write_disable_b:1;
+ unsigned write_disable_g:1;
+ unsigned write_disable_r:1;
+ unsigned write_disable_a:1;
+ unsigned pad3:1;
+ unsigned alpha_to_coverage_dither:1;
+ unsigned alpha_to_one:1;
+ unsigned alpha_to_coverage:1;
} blend1;
};
struct gen6_color_calc_state
{
struct {
- GLuint alpha_test_format:1;
- GLuint pad0:14;
- GLuint round_disable:1;
- GLuint bf_stencil_ref:8;
- GLuint stencil_ref:8;
+ unsigned alpha_test_format:1;
+ unsigned pad0:14;
+ unsigned round_disable:1;
+ unsigned bf_stencil_ref:8;
+ unsigned stencil_ref:8;
} cc0;
union {
- GLfloat alpha_ref_f;
+ float alpha_ref_f;
struct {
- GLuint ui:8;
- GLuint pad0:24;
+ unsigned ui:8;
+ unsigned pad0:24;
} alpha_ref_fi;
} cc1;
- GLfloat constant_r;
- GLfloat constant_g;
- GLfloat constant_b;
- GLfloat constant_a;
+ float constant_r;
+ float constant_g;
+ float constant_b;
+ float constant_a;
};
struct gen6_depth_stencil_state
{
struct {
- GLuint pad0:3;
- GLuint bf_stencil_pass_depth_pass_op:3;
- GLuint bf_stencil_pass_depth_fail_op:3;
- GLuint bf_stencil_fail_op:3;
- GLuint bf_stencil_func:3;
- GLuint bf_stencil_enable:1;
- GLuint pad1:2;
- GLuint stencil_write_enable:1;
- GLuint stencil_pass_depth_pass_op:3;
- GLuint stencil_pass_depth_fail_op:3;
- GLuint stencil_fail_op:3;
- GLuint stencil_func:3;
- GLuint stencil_enable:1;
+ unsigned pad0:3;
+ unsigned bf_stencil_pass_depth_pass_op:3;
+ unsigned bf_stencil_pass_depth_fail_op:3;
+ unsigned bf_stencil_fail_op:3;
+ unsigned bf_stencil_func:3;
+ unsigned bf_stencil_enable:1;
+ unsigned pad1:2;
+ unsigned stencil_write_enable:1;
+ unsigned stencil_pass_depth_pass_op:3;
+ unsigned stencil_pass_depth_fail_op:3;
+ unsigned stencil_fail_op:3;
+ unsigned stencil_func:3;
+ unsigned stencil_enable:1;
} ds0;
struct {
- GLuint bf_stencil_write_mask:8;
- GLuint bf_stencil_test_mask:8;
- GLuint stencil_write_mask:8;
- GLuint stencil_test_mask:8;
+ unsigned bf_stencil_write_mask:8;
+ unsigned bf_stencil_test_mask:8;
+ unsigned stencil_write_mask:8;
+ unsigned stencil_test_mask:8;
} ds1;
struct {
- GLuint pad0:26;
- GLuint depth_write_enable:1;
- GLuint depth_test_func:3;
- GLuint pad1:1;
- GLuint depth_test_enable:1;
+ unsigned pad0:26;
+ unsigned depth_write_enable:1;
+ unsigned depth_test_func:3;
+ unsigned pad1:1;
+ unsigned depth_test_enable:1;
} ds2;
};
@@ -300,90 +294,90 @@ struct brw_cc_unit_state
{
struct
{
- GLuint pad0:3;
- GLuint bf_stencil_pass_depth_pass_op:3;
- GLuint bf_stencil_pass_depth_fail_op:3;
- GLuint bf_stencil_fail_op:3;
- GLuint bf_stencil_func:3;
- GLuint bf_stencil_enable:1;
- GLuint pad1:2;
- GLuint stencil_write_enable:1;
- GLuint stencil_pass_depth_pass_op:3;
- GLuint stencil_pass_depth_fail_op:3;
- GLuint stencil_fail_op:3;
- GLuint stencil_func:3;
- GLuint stencil_enable:1;
+ unsigned pad0:3;
+ unsigned bf_stencil_pass_depth_pass_op:3;
+ unsigned bf_stencil_pass_depth_fail_op:3;
+ unsigned bf_stencil_fail_op:3;
+ unsigned bf_stencil_func:3;
+ unsigned bf_stencil_enable:1;
+ unsigned pad1:2;
+ unsigned stencil_write_enable:1;
+ unsigned stencil_pass_depth_pass_op:3;
+ unsigned stencil_pass_depth_fail_op:3;
+ unsigned stencil_fail_op:3;
+ unsigned stencil_func:3;
+ unsigned stencil_enable:1;
} cc0;
struct
{
- GLuint bf_stencil_ref:8;
- GLuint stencil_write_mask:8;
- GLuint stencil_test_mask:8;
- GLuint stencil_ref:8;
+ unsigned bf_stencil_ref:8;
+ unsigned stencil_write_mask:8;
+ unsigned stencil_test_mask:8;
+ unsigned stencil_ref:8;
} cc1;
struct
{
- GLuint logicop_enable:1;
- GLuint pad0:10;
- GLuint depth_write_enable:1;
- GLuint depth_test_function:3;
- GLuint depth_test:1;
- GLuint bf_stencil_write_mask:8;
- GLuint bf_stencil_test_mask:8;
+ unsigned logicop_enable:1;
+ unsigned pad0:10;
+ unsigned depth_write_enable:1;
+ unsigned depth_test_function:3;
+ unsigned depth_test:1;
+ unsigned bf_stencil_write_mask:8;
+ unsigned bf_stencil_test_mask:8;
} cc2;
struct
{
- GLuint pad0:8;
- GLuint alpha_test_func:3;
- GLuint alpha_test:1;
- GLuint blend_enable:1;
- GLuint ia_blend_enable:1;
- GLuint pad1:1;
- GLuint alpha_test_format:1;
- GLuint pad2:16;
+ unsigned pad0:8;
+ unsigned alpha_test_func:3;
+ unsigned alpha_test:1;
+ unsigned blend_enable:1;
+ unsigned ia_blend_enable:1;
+ unsigned pad1:1;
+ unsigned alpha_test_format:1;
+ unsigned pad2:16;
} cc3;
struct
{
- GLuint pad0:5;
- GLuint cc_viewport_state_offset:27; /* Offset from GENERAL_STATE_BASE */
+ unsigned pad0:5;
+ unsigned cc_viewport_state_offset:27; /* Offset from GENERAL_STATE_BASE */
} cc4;
struct
{
- GLuint pad0:2;
- GLuint ia_dest_blend_factor:5;
- GLuint ia_src_blend_factor:5;
- GLuint ia_blend_function:3;
- GLuint statistics_enable:1;
- GLuint logicop_func:4;
- GLuint pad1:11;
- GLuint dither_enable:1;
+ unsigned pad0:2;
+ unsigned ia_dest_blend_factor:5;
+ unsigned ia_src_blend_factor:5;
+ unsigned ia_blend_function:3;
+ unsigned statistics_enable:1;
+ unsigned logicop_func:4;
+ unsigned pad1:11;
+ unsigned dither_enable:1;
} cc5;
struct
{
- GLuint clamp_post_alpha_blend:1;
- GLuint clamp_pre_alpha_blend:1;
- GLuint clamp_range:2;
- GLuint pad0:11;
- GLuint y_dither_offset:2;
- GLuint x_dither_offset:2;
- GLuint dest_blend_factor:5;
- GLuint src_blend_factor:5;
- GLuint blend_function:3;
+ unsigned clamp_post_alpha_blend:1;
+ unsigned clamp_pre_alpha_blend:1;
+ unsigned clamp_range:2;
+ unsigned pad0:11;
+ unsigned y_dither_offset:2;
+ unsigned x_dither_offset:2;
+ unsigned dest_blend_factor:5;
+ unsigned src_blend_factor:5;
+ unsigned blend_function:3;
} cc6;
struct {
union {
- GLfloat f;
- GLubyte ub[4];
+ float f;
+ uint8_t ub[4];
} alpha_ref;
} cc7;
};
@@ -397,62 +391,62 @@ struct brw_sf_unit_state
struct
{
- GLuint pad0:10;
- GLuint stats_enable:1;
- GLuint nr_urb_entries:7;
- GLuint pad1:1;
- GLuint urb_entry_allocation_size:5;
- GLuint pad2:1;
- GLuint max_threads:6;
- GLuint pad3:1;
+ unsigned pad0:10;
+ unsigned stats_enable:1;
+ unsigned nr_urb_entries:7;
+ unsigned pad1:1;
+ unsigned urb_entry_allocation_size:5;
+ unsigned pad2:1;
+ unsigned max_threads:6;
+ unsigned pad3:1;
} thread4;
struct
{
- GLuint front_winding:1;
- GLuint viewport_transform:1;
- GLuint pad0:3;
- GLuint sf_viewport_state_offset:27; /* Offset from GENERAL_STATE_BASE */
+ unsigned front_winding:1;
+ unsigned viewport_transform:1;
+ unsigned pad0:3;
+ unsigned sf_viewport_state_offset:27; /* Offset from GENERAL_STATE_BASE */
} sf5;
struct
{
- GLuint pad0:9;
- GLuint dest_org_vbias:4;
- GLuint dest_org_hbias:4;
- GLuint scissor:1;
- GLuint disable_2x2_trifilter:1;
- GLuint disable_zero_pix_trifilter:1;
- GLuint point_rast_rule:2;
- GLuint line_endcap_aa_region_width:2;
- GLuint line_width:4;
- GLuint fast_scissor_disable:1;
- GLuint cull_mode:2;
- GLuint aa_enable:1;
+ unsigned pad0:9;
+ unsigned dest_org_vbias:4;
+ unsigned dest_org_hbias:4;
+ unsigned scissor:1;
+ unsigned disable_2x2_trifilter:1;
+ unsigned disable_zero_pix_trifilter:1;
+ unsigned point_rast_rule:2;
+ unsigned line_endcap_aa_region_width:2;
+ unsigned line_width:4;
+ unsigned fast_scissor_disable:1;
+ unsigned cull_mode:2;
+ unsigned aa_enable:1;
} sf6;
struct
{
- GLuint point_size:11;
- GLuint use_point_size_state:1;
- GLuint subpixel_precision:1;
- GLuint sprite_point:1;
- GLuint pad0:10;
- GLuint aa_line_distance_mode:1;
- GLuint trifan_pv:2;
- GLuint linestrip_pv:2;
- GLuint tristrip_pv:2;
- GLuint line_last_pixel_enable:1;
+ unsigned point_size:11;
+ unsigned use_point_size_state:1;
+ unsigned subpixel_precision:1;
+ unsigned sprite_point:1;
+ unsigned pad0:10;
+ unsigned aa_line_distance_mode:1;
+ unsigned trifan_pv:2;
+ unsigned linestrip_pv:2;
+ unsigned tristrip_pv:2;
+ unsigned line_last_pixel_enable:1;
} sf7;
};
struct gen6_scissor_rect
{
- GLuint xmin:16;
- GLuint ymin:16;
- GLuint xmax:16;
- GLuint ymax:16;
+ unsigned xmin:16;
+ unsigned ymin:16;
+ unsigned xmax:16;
+ unsigned ymax:16;
};
struct brw_gs_unit_state
@@ -464,37 +458,37 @@ struct brw_gs_unit_state
struct
{
- GLuint pad0:8;
- GLuint rendering_enable:1; /* for Ironlake */
- GLuint pad4:1;
- GLuint stats_enable:1;
- GLuint nr_urb_entries:7;
- GLuint pad1:1;
- GLuint urb_entry_allocation_size:5;
- GLuint pad2:1;
- GLuint max_threads:5;
- GLuint pad3:2;
+ unsigned pad0:8;
+ unsigned rendering_enable:1; /* for Ironlake */
+ unsigned pad4:1;
+ unsigned stats_enable:1;
+ unsigned nr_urb_entries:7;
+ unsigned pad1:1;
+ unsigned urb_entry_allocation_size:5;
+ unsigned pad2:1;
+ unsigned max_threads:5;
+ unsigned pad3:2;
} thread4;
struct
{
- GLuint sampler_count:3;
- GLuint pad0:2;
- GLuint sampler_state_pointer:27;
+ unsigned sampler_count:3;
+ unsigned pad0:2;
+ unsigned sampler_state_pointer:27;
} gs5;
struct
{
- GLuint max_vp_index:4;
- GLuint pad0:12;
- GLuint svbi_post_inc_value:10;
- GLuint pad1:1;
- GLuint svbi_post_inc_enable:1;
- GLuint svbi_payload:1;
- GLuint discard_adjaceny:1;
- GLuint reorder_enable:1;
- GLuint pad2:1;
+ unsigned max_vp_index:4;
+ unsigned pad0:12;
+ unsigned svbi_post_inc_value:10;
+ unsigned pad1:1;
+ unsigned svbi_post_inc_enable:1;
+ unsigned svbi_payload:1;
+ unsigned discard_adjaceny:1;
+ unsigned reorder_enable:1;
+ unsigned pad2:1;
} gs6;
};
@@ -508,28 +502,28 @@ struct brw_vs_unit_state
struct
{
- GLuint pad0:10;
- GLuint stats_enable:1;
- GLuint nr_urb_entries:7;
- GLuint pad1:1;
- GLuint urb_entry_allocation_size:5;
- GLuint pad2:1;
- GLuint max_threads:6;
- GLuint pad3:1;
+ unsigned pad0:10;
+ unsigned stats_enable:1;
+ unsigned nr_urb_entries:7;
+ unsigned pad1:1;
+ unsigned urb_entry_allocation_size:5;
+ unsigned pad2:1;
+ unsigned max_threads:6;
+ unsigned pad3:1;
} thread4;
struct
{
- GLuint sampler_count:3;
- GLuint pad0:2;
- GLuint sampler_state_pointer:27;
+ unsigned sampler_count:3;
+ unsigned pad0:2;
+ unsigned sampler_state_pointer:27;
} vs5;
struct
{
- GLuint vs_enable:1;
- GLuint vert_cache_disable:1;
- GLuint pad0:30;
+ unsigned vs_enable:1;
+ unsigned vert_cache_disable:1;
+ unsigned pad0:30;
} vs6;
};
@@ -542,71 +536,71 @@ struct brw_wm_unit_state
struct thread3 thread3;
struct {
- GLuint stats_enable:1;
- GLuint depth_buffer_clear:1;
- GLuint sampler_count:3;
- GLuint sampler_state_pointer:27;
+ unsigned stats_enable:1;
+ unsigned depth_buffer_clear:1;
+ unsigned sampler_count:3;
+ unsigned sampler_state_pointer:27;
} wm4;
struct
{
- GLuint enable_8_pix:1;
- GLuint enable_16_pix:1;
- GLuint enable_32_pix:1;
- GLuint enable_con_32_pix:1;
- GLuint enable_con_64_pix:1;
- GLuint pad0:1;
+ unsigned enable_8_pix:1;
+ unsigned enable_16_pix:1;
+ unsigned enable_32_pix:1;
+ unsigned enable_con_32_pix:1;
+ unsigned enable_con_64_pix:1;
+ unsigned pad0:1;
/* These next four bits are for Ironlake+ */
- GLuint fast_span_coverage_enable:1;
- GLuint depth_buffer_clear:1;
- GLuint depth_buffer_resolve_enable:1;
- GLuint hierarchical_depth_buffer_resolve_enable:1;
-
- GLuint legacy_global_depth_bias:1;
- GLuint line_stipple:1;
- GLuint depth_offset:1;
- GLuint polygon_stipple:1;
- GLuint line_aa_region_width:2;
- GLuint line_endcap_aa_region_width:2;
- GLuint early_depth_test:1;
- GLuint thread_dispatch_enable:1;
- GLuint program_uses_depth:1;
- GLuint program_computes_depth:1;
- GLuint program_uses_killpixel:1;
- GLuint legacy_line_rast: 1;
- GLuint transposed_urb_read_enable:1;
- GLuint max_threads:7;
+ unsigned fast_span_coverage_enable:1;
+ unsigned depth_buffer_clear:1;
+ unsigned depth_buffer_resolve_enable:1;
+ unsigned hierarchical_depth_buffer_resolve_enable:1;
+
+ unsigned legacy_global_depth_bias:1;
+ unsigned line_stipple:1;
+ unsigned depth_offset:1;
+ unsigned polygon_stipple:1;
+ unsigned line_aa_region_width:2;
+ unsigned line_endcap_aa_region_width:2;
+ unsigned early_depth_test:1;
+ unsigned thread_dispatch_enable:1;
+ unsigned program_uses_depth:1;
+ unsigned program_computes_depth:1;
+ unsigned program_uses_killpixel:1;
+ unsigned legacy_line_rast: 1;
+ unsigned transposed_urb_read_enable:1;
+ unsigned max_threads:7;
} wm5;
- GLfloat global_depth_offset_constant;
- GLfloat global_depth_offset_scale;
+ float global_depth_offset_constant;
+ float global_depth_offset_scale;
/* for Ironlake only */
struct {
- GLuint pad0:1;
- GLuint grf_reg_count_1:3;
- GLuint pad1:2;
- GLuint kernel_start_pointer_1:26;
+ unsigned pad0:1;
+ unsigned grf_reg_count_1:3;
+ unsigned pad1:2;
+ unsigned kernel_start_pointer_1:26;
} wm8;
struct {
- GLuint pad0:1;
- GLuint grf_reg_count_2:3;
- GLuint pad1:2;
- GLuint kernel_start_pointer_2:26;
+ unsigned pad0:1;
+ unsigned grf_reg_count_2:3;
+ unsigned pad1:2;
+ unsigned kernel_start_pointer_2:26;
} wm9;
struct {
- GLuint pad0:1;
- GLuint grf_reg_count_3:3;
- GLuint pad1:2;
- GLuint kernel_start_pointer_3:26;
+ unsigned pad0:1;
+ unsigned grf_reg_count_3:3;
+ unsigned pad1:2;
+ unsigned kernel_start_pointer_3:26;
} wm10;
};
struct brw_sampler_default_color {
- GLfloat color[4];
+ float color[4];
};
struct gen5_sampler_default_color {
@@ -623,48 +617,48 @@ struct brw_sampler_state
struct
{
- GLuint shadow_function:3;
- GLuint lod_bias:11;
- GLuint min_filter:3;
- GLuint mag_filter:3;
- GLuint mip_filter:2;
- GLuint base_level:5;
- GLuint min_mag_neq:1;
- GLuint lod_preclamp:1;
- GLuint default_color_mode:1;
- GLuint pad0:1;
- GLuint disable:1;
+ unsigned shadow_function:3;
+ unsigned lod_bias:11;
+ unsigned min_filter:3;
+ unsigned mag_filter:3;
+ unsigned mip_filter:2;
+ unsigned base_level:5;
+ unsigned min_mag_neq:1;
+ unsigned lod_preclamp:1;
+ unsigned default_color_mode:1;
+ unsigned pad0:1;
+ unsigned disable:1;
} ss0;
struct
{
- GLuint r_wrap_mode:3;
- GLuint t_wrap_mode:3;
- GLuint s_wrap_mode:3;
- GLuint cube_control_mode:1;
- GLuint pad:2;
- GLuint max_lod:10;
- GLuint min_lod:10;
+ unsigned r_wrap_mode:3;
+ unsigned t_wrap_mode:3;
+ unsigned s_wrap_mode:3;
+ unsigned cube_control_mode:1;
+ unsigned pad:2;
+ unsigned max_lod:10;
+ unsigned min_lod:10;
} ss1;
struct
{
- GLuint pad:5;
- GLuint default_color_pointer:27;
+ unsigned pad:5;
+ unsigned default_color_pointer:27;
} ss2;
struct
{
- GLuint non_normalized_coord:1;
- GLuint pad:12;
- GLuint address_round:6;
- GLuint max_aniso:3;
- GLuint chroma_key_mode:1;
- GLuint chroma_key_index:2;
- GLuint chroma_key_enable:1;
- GLuint monochrome_filter_width:3;
- GLuint monochrome_filter_height:3;
+ unsigned non_normalized_coord:1;
+ unsigned pad:12;
+ unsigned address_round:6;
+ unsigned max_aniso:3;
+ unsigned chroma_key_mode:1;
+ unsigned chroma_key_index:2;
+ unsigned chroma_key_enable:1;
+ unsigned monochrome_filter_width:3;
+ unsigned monochrome_filter_height:3;
} ss3;
};
@@ -672,152 +666,152 @@ struct gen7_sampler_state
{
struct
{
- GLuint aniso_algorithm:1;
- GLuint lod_bias:13;
- GLuint min_filter:3;
- GLuint mag_filter:3;
- GLuint mip_filter:2;
- GLuint base_level:5;
- GLuint pad1:1;
- GLuint lod_preclamp:1;
- GLuint default_color_mode:1;
- GLuint pad0:1;
- GLuint disable:1;
+ unsigned aniso_algorithm:1;
+ unsigned lod_bias:13;
+ unsigned min_filter:3;
+ unsigned mag_filter:3;
+ unsigned mip_filter:2;
+ unsigned base_level:5;
+ unsigned pad1:1;
+ unsigned lod_preclamp:1;
+ unsigned default_color_mode:1;
+ unsigned pad0:1;
+ unsigned disable:1;
} ss0;
struct
{
- GLuint cube_control_mode:1;
- GLuint shadow_function:3;
- GLuint pad:4;
- GLuint max_lod:12;
- GLuint min_lod:12;
+ unsigned cube_control_mode:1;
+ unsigned shadow_function:3;
+ unsigned pad:4;
+ unsigned max_lod:12;
+ unsigned min_lod:12;
} ss1;
struct
{
- GLuint pad:5;
- GLuint default_color_pointer:27;
+ unsigned pad:5;
+ unsigned default_color_pointer:27;
} ss2;
struct
{
- GLuint r_wrap_mode:3;
- GLuint t_wrap_mode:3;
- GLuint s_wrap_mode:3;
- GLuint pad:1;
- GLuint non_normalized_coord:1;
- GLuint trilinear_quality:2;
- GLuint address_round:6;
- GLuint max_aniso:3;
- GLuint chroma_key_mode:1;
- GLuint chroma_key_index:2;
- GLuint chroma_key_enable:1;
- GLuint pad0:6;
+ unsigned r_wrap_mode:3;
+ unsigned t_wrap_mode:3;
+ unsigned s_wrap_mode:3;
+ unsigned pad:1;
+ unsigned non_normalized_coord:1;
+ unsigned trilinear_quality:2;
+ unsigned address_round:6;
+ unsigned max_aniso:3;
+ unsigned chroma_key_mode:1;
+ unsigned chroma_key_index:2;
+ unsigned chroma_key_enable:1;
+ unsigned pad0:6;
} ss3;
};
struct brw_clipper_viewport
{
- GLfloat xmin;
- GLfloat xmax;
- GLfloat ymin;
- GLfloat ymax;
+ float xmin;
+ float xmax;
+ float ymin;
+ float ymax;
};
struct brw_cc_viewport
{
- GLfloat min_depth;
- GLfloat max_depth;
+ float min_depth;
+ float max_depth;
};
struct brw_sf_viewport
{
struct {
- GLfloat m00;
- GLfloat m11;
- GLfloat m22;
- GLfloat m30;
- GLfloat m31;
- GLfloat m32;
+ float m00;
+ float m11;
+ float m22;
+ float m30;
+ float m31;
+ float m32;
} viewport;
/* scissor coordinates are inclusive */
struct {
- GLshort xmin;
- GLshort ymin;
- GLshort xmax;
- GLshort ymax;
+ int16_t xmin;
+ int16_t ymin;
+ int16_t xmax;
+ int16_t ymax;
} scissor;
};
struct gen6_sf_viewport {
- GLfloat m00;
- GLfloat m11;
- GLfloat m22;
- GLfloat m30;
- GLfloat m31;
- GLfloat m32;
+ float m00;
+ float m11;
+ float m22;
+ float m30;
+ float m31;
+ float m32;
};
struct gen7_sf_clip_viewport {
struct {
- GLfloat m00;
- GLfloat m11;
- GLfloat m22;
- GLfloat m30;
- GLfloat m31;
- GLfloat m32;
+ float m00;
+ float m11;
+ float m22;
+ float m30;
+ float m31;
+ float m32;
} viewport;
- GLuint pad0[2];
+ unsigned pad0[2];
struct {
- GLfloat xmin;
- GLfloat xmax;
- GLfloat ymin;
- GLfloat ymax;
+ float xmin;
+ float xmax;
+ float ymin;
+ float ymax;
} guardband;
- GLfloat pad1[4];
+ float pad1[4];
};
struct brw_vertex_element_state
{
struct
{
- GLuint src_offset:11;
- GLuint pad:5;
- GLuint src_format:9;
- GLuint pad0:1;
- GLuint valid:1;
- GLuint vertex_buffer_index:5;
+ unsigned src_offset:11;
+ unsigned pad:5;
+ unsigned src_format:9;
+ unsigned pad0:1;
+ unsigned valid:1;
+ unsigned vertex_buffer_index:5;
} ve0;
struct
{
- GLuint dst_offset:8;
- GLuint pad:8;
- GLuint vfcomponent3:4;
- GLuint vfcomponent2:4;
- GLuint vfcomponent1:4;
- GLuint vfcomponent0:4;
+ unsigned dst_offset:8;
+ unsigned pad:8;
+ unsigned vfcomponent3:4;
+ unsigned vfcomponent2:4;
+ unsigned vfcomponent1:4;
+ unsigned vfcomponent0:4;
} ve1;
};
struct brw_urb_immediate {
- GLuint opcode:4;
- GLuint offset:6;
- GLuint swizzle_control:2;
- GLuint pad:1;
- GLuint allocate:1;
- GLuint used:1;
- GLuint complete:1;
- GLuint response_length:4;
- GLuint msg_length:4;
- GLuint msg_target:4;
- GLuint pad1:3;
- GLuint end_of_thread:1;
+ unsigned opcode:4;
+ unsigned offset:6;
+ unsigned swizzle_control:2;
+ unsigned pad:1;
+ unsigned allocate:1;
+ unsigned used:1;
+ unsigned complete:1;
+ unsigned response_length:4;
+ unsigned msg_length:4;
+ unsigned msg_target:4;
+ unsigned pad1:3;
+ unsigned end_of_thread:1;
};
/* Instruction format for the execution units:
@@ -827,119 +821,119 @@ struct brw_instruction
{
struct
{
- GLuint opcode:7;
- GLuint pad:1;
- GLuint access_mode:1;
- GLuint mask_control:1;
- GLuint dependency_control:2;
- GLuint compression_control:2; /* gen6: quater control */
- GLuint thread_control:2;
- GLuint predicate_control:4;
- GLuint predicate_inverse:1;
- GLuint execution_size:3;
+ unsigned opcode:7;
+ unsigned pad:1;
+ unsigned access_mode:1;
+ unsigned mask_control:1;
+ unsigned dependency_control:2;
+ unsigned compression_control:2; /* gen6: quater control */
+ unsigned thread_control:2;
+ unsigned predicate_control:4;
+ unsigned predicate_inverse:1;
+ unsigned execution_size:3;
/**
* Conditional Modifier for most instructions. On Gen6+, this is also
* used for the SEND instruction's Message Target/SFID.
*/
- GLuint destreg__conditionalmod:4;
- GLuint acc_wr_control:1;
- GLuint cmpt_control:1;
- GLuint debug_control:1;
- GLuint saturate:1;
+ unsigned destreg__conditionalmod:4;
+ unsigned acc_wr_control:1;
+ unsigned cmpt_control:1;
+ unsigned debug_control:1;
+ unsigned saturate:1;
} header;
union {
struct
{
- GLuint dest_reg_file:2;
- GLuint dest_reg_type:3;
- GLuint src0_reg_file:2;
- GLuint src0_reg_type:3;
- GLuint src1_reg_file:2;
- GLuint src1_reg_type:3;
- GLuint pad:1;
- GLuint dest_subreg_nr:5;
- GLuint dest_reg_nr:8;
- GLuint dest_horiz_stride:2;
- GLuint dest_address_mode:1;
+ unsigned dest_reg_file:2;
+ unsigned dest_reg_type:3;
+ unsigned src0_reg_file:2;
+ unsigned src0_reg_type:3;
+ unsigned src1_reg_file:2;
+ unsigned src1_reg_type:3;
+ unsigned pad:1;
+ unsigned dest_subreg_nr:5;
+ unsigned dest_reg_nr:8;
+ unsigned dest_horiz_stride:2;
+ unsigned dest_address_mode:1;
} da1;
struct
{
- GLuint dest_reg_file:2;
- GLuint dest_reg_type:3;
- GLuint src0_reg_file:2;
- GLuint src0_reg_type:3;
- GLuint src1_reg_file:2; /* 0x00000c00 */
- GLuint src1_reg_type:3; /* 0x00007000 */
- GLuint pad:1;
- GLint dest_indirect_offset:10; /* offset against the deref'd address reg */
- GLuint dest_subreg_nr:3; /* subnr for the address reg a0.x */
- GLuint dest_horiz_stride:2;
- GLuint dest_address_mode:1;
+ unsigned dest_reg_file:2;
+ unsigned dest_reg_type:3;
+ unsigned src0_reg_file:2;
+ unsigned src0_reg_type:3;
+ unsigned src1_reg_file:2; /* 0x00000c00 */
+ unsigned src1_reg_type:3; /* 0x00007000 */
+ unsigned pad:1;
+ int dest_indirect_offset:10; /* offset against the deref'd address reg */
+ unsigned dest_subreg_nr:3; /* subnr for the address reg a0.x */
+ unsigned dest_horiz_stride:2;
+ unsigned dest_address_mode:1;
} ia1;
struct
{
- GLuint dest_reg_file:2;
- GLuint dest_reg_type:3;
- GLuint src0_reg_file:2;
- GLuint src0_reg_type:3;
- GLuint src1_reg_file:2;
- GLuint src1_reg_type:3;
- GLuint pad:1;
- GLuint dest_writemask:4;
- GLuint dest_subreg_nr:1;
- GLuint dest_reg_nr:8;
- GLuint dest_horiz_stride:2;
- GLuint dest_address_mode:1;
+ unsigned dest_reg_file:2;
+ unsigned dest_reg_type:3;
+ unsigned src0_reg_file:2;
+ unsigned src0_reg_type:3;
+ unsigned src1_reg_file:2;
+ unsigned src1_reg_type:3;
+ unsigned pad:1;
+ unsigned dest_writemask:4;
+ unsigned dest_subreg_nr:1;
+ unsigned dest_reg_nr:8;
+ unsigned dest_horiz_stride:2;
+ unsigned dest_address_mode:1;
} da16;
struct
{
- GLuint dest_reg_file:2;
- GLuint dest_reg_type:3;
- GLuint src0_reg_file:2;
- GLuint src0_reg_type:3;
- GLuint pad0:6;
- GLuint dest_writemask:4;
- GLint dest_indirect_offset:6;
- GLuint dest_subreg_nr:3;
- GLuint dest_horiz_stride:2;
- GLuint dest_address_mode:1;
+ unsigned dest_reg_file:2;
+ unsigned dest_reg_type:3;
+ unsigned src0_reg_file:2;
+ unsigned src0_reg_type:3;
+ unsigned pad0:6;
+ unsigned dest_writemask:4;
+ int dest_indirect_offset:6;
+ unsigned dest_subreg_nr:3;
+ unsigned dest_horiz_stride:2;
+ unsigned dest_address_mode:1;
} ia16;
struct {
- GLuint dest_reg_file:2;
- GLuint dest_reg_type:3;
- GLuint src0_reg_file:2;
- GLuint src0_reg_type:3;
- GLuint src1_reg_file:2;
- GLuint src1_reg_type:3;
- GLuint pad:1;
-
- GLint jump_count:16;
+ unsigned dest_reg_file:2;
+ unsigned dest_reg_type:3;
+ unsigned src0_reg_file:2;
+ unsigned src0_reg_type:3;
+ unsigned src1_reg_file:2;
+ unsigned src1_reg_type:3;
+ unsigned pad:1;
+
+ int jump_count:16;
} branch_gen6;
struct {
- GLuint dest_reg_file:1;
- GLuint flag_subreg_nr:1;
- GLuint flag_reg_nr:1;
- GLuint pad0:1;
- GLuint src0_abs:1;
- GLuint src0_negate:1;
- GLuint src1_abs:1;
- GLuint src1_negate:1;
- GLuint src2_abs:1;
- GLuint src2_negate:1;
- GLuint src_reg_type:2;
- GLuint dest_reg_type:2;
- GLuint pad1:1;
- GLuint nib_ctrl:1;
- GLuint pad2:1;
- GLuint dest_writemask:4;
- GLuint dest_subreg_nr:3;
- GLuint dest_reg_nr:8;
+ unsigned dest_reg_file:1;
+ unsigned flag_subreg_nr:1;
+ unsigned flag_reg_nr:1;
+ unsigned pad0:1;
+ unsigned src0_abs:1;
+ unsigned src0_negate:1;
+ unsigned src1_abs:1;
+ unsigned src1_negate:1;
+ unsigned src2_abs:1;
+ unsigned src2_negate:1;
+ unsigned src_reg_type:2;
+ unsigned dest_reg_type:2;
+ unsigned pad1:1;
+ unsigned nib_ctrl:1;
+ unsigned pad2:1;
+ unsigned dest_writemask:4;
+ unsigned dest_subreg_nr:3;
+ unsigned dest_reg_nr:8;
} da3src;
uint32_t ud;
@@ -949,68 +943,68 @@ struct brw_instruction
union {
struct
{
- GLuint src0_subreg_nr:5;
- GLuint src0_reg_nr:8;
- GLuint src0_abs:1;
- GLuint src0_negate:1;
- GLuint src0_address_mode:1;
- GLuint src0_horiz_stride:2;
- GLuint src0_width:3;
- GLuint src0_vert_stride:4;
- GLuint flag_subreg_nr:1;
- GLuint flag_reg_nr:1;
- GLuint pad:5;
+ unsigned src0_subreg_nr:5;
+ unsigned src0_reg_nr:8;
+ unsigned src0_abs:1;
+ unsigned src0_negate:1;
+ unsigned src0_address_mode:1;
+ unsigned src0_horiz_stride:2;
+ unsigned src0_width:3;
+ unsigned src0_vert_stride:4;
+ unsigned flag_subreg_nr:1;
+ unsigned flag_reg_nr:1;
+ unsigned pad:5;
} da1;
struct
{
- GLint src0_indirect_offset:10;
- GLuint src0_subreg_nr:3;
- GLuint src0_abs:1;
- GLuint src0_negate:1;
- GLuint src0_address_mode:1;
- GLuint src0_horiz_stride:2;
- GLuint src0_width:3;
- GLuint src0_vert_stride:4;
- GLuint flag_subreg_nr:1;
- GLuint flag_reg_nr:1;
- GLuint pad:5;
+ int src0_indirect_offset:10;
+ unsigned src0_subreg_nr:3;
+ unsigned src0_abs:1;
+ unsigned src0_negate:1;
+ unsigned src0_address_mode:1;
+ unsigned src0_horiz_stride:2;
+ unsigned src0_width:3;
+ unsigned src0_vert_stride:4;
+ unsigned flag_subreg_nr:1;
+ unsigned flag_reg_nr:1;
+ unsigned pad:5;
} ia1;
struct
{
- GLuint src0_swz_x:2;
- GLuint src0_swz_y:2;
- GLuint src0_subreg_nr:1;
- GLuint src0_reg_nr:8;
- GLuint src0_abs:1;
- GLuint src0_negate:1;
- GLuint src0_address_mode:1;
- GLuint src0_swz_z:2;
- GLuint src0_swz_w:2;
- GLuint pad0:1;
- GLuint src0_vert_stride:4;
- GLuint flag_subreg_nr:1;
- GLuint flag_reg_nr:1;
- GLuint pad1:5;
+ unsigned src0_swz_x:2;
+ unsigned src0_swz_y:2;
+ unsigned src0_subreg_nr:1;
+ unsigned src0_reg_nr:8;
+ unsigned src0_abs:1;
+ unsigned src0_negate:1;
+ unsigned src0_address_mode:1;
+ unsigned src0_swz_z:2;
+ unsigned src0_swz_w:2;
+ unsigned pad0:1;
+ unsigned src0_vert_stride:4;
+ unsigned flag_subreg_nr:1;
+ unsigned flag_reg_nr:1;
+ unsigned pad1:5;
} da16;
struct
{
- GLuint src0_swz_x:2;
- GLuint src0_swz_y:2;
- GLint src0_indirect_offset:6;
- GLuint src0_subreg_nr:3;
- GLuint src0_abs:1;
- GLuint src0_negate:1;
- GLuint src0_address_mode:1;
- GLuint src0_swz_z:2;
- GLuint src0_swz_w:2;
- GLuint pad0:1;
- GLuint src0_vert_stride:4;
- GLuint flag_subreg_nr:1;
- GLuint flag_reg_nr:1;
- GLuint pad1:5;
+ unsigned src0_swz_x:2;
+ unsigned src0_swz_y:2;
+ int src0_indirect_offset:6;
+ unsigned src0_subreg_nr:3;
+ unsigned src0_abs:1;
+ unsigned src0_negate:1;
+ unsigned src0_address_mode:1;
+ unsigned src0_swz_z:2;
+ unsigned src0_swz_w:2;
+ unsigned pad0:1;
+ unsigned src0_vert_stride:4;
+ unsigned flag_subreg_nr:1;
+ unsigned flag_reg_nr:1;
+ unsigned pad1:5;
} ia16;
/* Extended Message Descriptor for Ironlake (Gen5) SEND instruction.
@@ -1020,21 +1014,21 @@ struct brw_instruction
*/
struct
{
- GLuint pad:26;
- GLuint end_of_thread:1;
- GLuint pad1:1;
- GLuint sfid:4;
+ unsigned pad:26;
+ unsigned end_of_thread:1;
+ unsigned pad1:1;
+ unsigned sfid:4;
} send_gen5; /* for Ironlake only */
struct {
- GLuint src0_rep_ctrl:1;
- GLuint src0_swizzle:8;
- GLuint src0_subreg_nr:3;
- GLuint src0_reg_nr:8;
- GLuint pad0:1;
- GLuint src1_rep_ctrl:1;
- GLuint src1_swizzle:8;
- GLuint src1_subreg_nr_low:2;
+ unsigned src0_rep_ctrl:1;
+ unsigned src0_swizzle:8;
+ unsigned src0_subreg_nr:3;
+ unsigned src0_reg_nr:8;
+ unsigned pad0:1;
+ unsigned src1_rep_ctrl:1;
+ unsigned src1_swizzle:8;
+ unsigned src1_subreg_nr_low:2;
} da3src;
uint32_t ud;
@@ -1044,68 +1038,68 @@ struct brw_instruction
{
struct
{
- GLuint src1_subreg_nr:5;
- GLuint src1_reg_nr:8;
- GLuint src1_abs:1;
- GLuint src1_negate:1;
- GLuint src1_address_mode:1;
- GLuint src1_horiz_stride:2;
- GLuint src1_width:3;
- GLuint src1_vert_stride:4;
- GLuint pad0:7;
+ unsigned src1_subreg_nr:5;
+ unsigned src1_reg_nr:8;
+ unsigned src1_abs:1;
+ unsigned src1_negate:1;
+ unsigned src1_address_mode:1;
+ unsigned src1_horiz_stride:2;
+ unsigned src1_width:3;
+ unsigned src1_vert_stride:4;
+ unsigned pad0:7;
} da1;
struct
{
- GLuint src1_swz_x:2;
- GLuint src1_swz_y:2;
- GLuint src1_subreg_nr:1;
- GLuint src1_reg_nr:8;
- GLuint src1_abs:1;
- GLuint src1_negate:1;
- GLuint src1_address_mode:1;
- GLuint src1_swz_z:2;
- GLuint src1_swz_w:2;
- GLuint pad1:1;
- GLuint src1_vert_stride:4;
- GLuint pad2:7;
+ unsigned src1_swz_x:2;
+ unsigned src1_swz_y:2;
+ unsigned src1_subreg_nr:1;
+ unsigned src1_reg_nr:8;
+ unsigned src1_abs:1;
+ unsigned src1_negate:1;
+ unsigned src1_address_mode:1;
+ unsigned src1_swz_z:2;
+ unsigned src1_swz_w:2;
+ unsigned pad1:1;
+ unsigned src1_vert_stride:4;
+ unsigned pad2:7;
} da16;
struct
{
- GLint src1_indirect_offset:10;
- GLuint src1_subreg_nr:3;
- GLuint src1_abs:1;
- GLuint src1_negate:1;
- GLuint src1_address_mode:1;
- GLuint src1_horiz_stride:2;
- GLuint src1_width:3;
- GLuint src1_vert_stride:4;
- GLuint pad1:7;
+ int src1_indirect_offset:10;
+ unsigned src1_subreg_nr:3;
+ unsigned src1_abs:1;
+ unsigned src1_negate:1;
+ unsigned src1_address_mode:1;
+ unsigned src1_horiz_stride:2;
+ unsigned src1_width:3;
+ unsigned src1_vert_stride:4;
+ unsigned pad1:7;
} ia1;
struct
{
- GLuint src1_swz_x:2;
- GLuint src1_swz_y:2;
- GLint src1_indirect_offset:6;
- GLuint src1_subreg_nr:3;
- GLuint src1_abs:1;
- GLuint src1_negate:1;
- GLuint src1_address_mode:1;
- GLuint src1_swz_z:2;
- GLuint src1_swz_w:2;
- GLuint pad1:1;
- GLuint src1_vert_stride:4;
- GLuint pad2:7;
+ unsigned src1_swz_x:2;
+ unsigned src1_swz_y:2;
+ int src1_indirect_offset:6;
+ unsigned src1_subreg_nr:3;
+ unsigned src1_abs:1;
+ unsigned src1_negate:1;
+ unsigned src1_address_mode:1;
+ unsigned src1_swz_z:2;
+ unsigned src1_swz_w:2;
+ unsigned pad1:1;
+ unsigned src1_vert_stride:4;
+ unsigned pad2:7;
} ia16;
struct
{
- GLint jump_count:16; /* note: signed */
- GLuint pop_count:4;
- GLuint pad0:12;
+ int jump_count:16; /* note: signed */
+ unsigned pop_count:4;
+ unsigned pad0:12;
} if_else;
/* This is also used for gen7 IF/ELSE instructions */
@@ -1124,7 +1118,7 @@ struct brw_instruction
int uip:16;
} break_cont;
- GLint JIP; /* used by Gen6 CALL instructions; Gen7 JMPI */
+ int JIP; /* used by Gen6 CALL instructions; Gen7 JMPI */
/**
* \defgroup SEND instructions / Message Descriptors
@@ -1140,12 +1134,12 @@ struct brw_instruction
* See the G45 PRM, Volume 4, Table 14-15.
*/
struct {
- GLuint function_control:16;
- GLuint response_length:4;
- GLuint msg_length:4;
- GLuint msg_target:4;
- GLuint pad1:3;
- GLuint end_of_thread:1;
+ unsigned function_control:16;
+ unsigned response_length:4;
+ unsigned msg_length:4;
+ unsigned msg_target:4;
+ unsigned pad1:3;
+ unsigned end_of_thread:1;
} generic;
/**
@@ -1161,238 +1155,238 @@ struct brw_instruction
* bit 127 of the instruction word"...which is bit 31 of this field.
*/
struct {
- GLuint function_control:19;
- GLuint header_present:1;
- GLuint response_length:5;
- GLuint msg_length:4;
- GLuint pad1:2;
- GLuint end_of_thread:1;
+ unsigned function_control:19;
+ unsigned header_present:1;
+ unsigned response_length:5;
+ unsigned msg_length:4;
+ unsigned pad1:2;
+ unsigned end_of_thread:1;
} generic_gen5;
struct {
- GLuint opcode:1;
- GLuint requester_type:1;
- GLuint pad:2;
- GLuint resource_select:1;
- GLuint pad1:11;
- GLuint response_length:4;
- GLuint msg_length:4;
- GLuint msg_target:4;
- GLuint pad2:3;
- GLuint end_of_thread:1;
+ unsigned opcode:1;
+ unsigned requester_type:1;
+ unsigned pad:2;
+ unsigned resource_select:1;
+ unsigned pad1:11;
+ unsigned response_length:4;
+ unsigned msg_length:4;
+ unsigned msg_target:4;
+ unsigned pad2:3;
+ unsigned end_of_thread:1;
} thread_spawner;
struct {
- GLuint opcode:1;
- GLuint requester_type:1;
- GLuint pad0:2;
- GLuint resource_select:1;
- GLuint pad1:14;
- GLuint header_present:1;
- GLuint response_length:5;
- GLuint msg_length:4;
- GLuint pad2:2;
- GLuint end_of_thread:1;
+ unsigned opcode:1;
+ unsigned requester_type:1;
+ unsigned pad0:2;
+ unsigned resource_select:1;
+ unsigned pad1:14;
+ unsigned header_present:1;
+ unsigned response_length:5;
+ unsigned msg_length:4;
+ unsigned pad2:2;
+ unsigned end_of_thread:1;
} thread_spawner_gen5;
/** G45 PRM, Volume 4, Section 6.1.1.1 */
struct {
- GLuint function:4;
- GLuint int_type:1;
- GLuint precision:1;
- GLuint saturate:1;
- GLuint data_type:1;
- GLuint pad0:8;
- GLuint response_length:4;
- GLuint msg_length:4;
- GLuint msg_target:4;
- GLuint pad1:3;
- GLuint end_of_thread:1;
+ unsigned function:4;
+ unsigned int_type:1;
+ unsigned precision:1;
+ unsigned saturate:1;
+ unsigned data_type:1;
+ unsigned pad0:8;
+ unsigned response_length:4;
+ unsigned msg_length:4;
+ unsigned msg_target:4;
+ unsigned pad1:3;
+ unsigned end_of_thread:1;
} math;
/** Ironlake PRM, Volume 4 Part 1, Section 6.1.1.1 */
struct {
- GLuint function:4;
- GLuint int_type:1;
- GLuint precision:1;
- GLuint saturate:1;
- GLuint data_type:1;
- GLuint snapshot:1;
- GLuint pad0:10;
- GLuint header_present:1;
- GLuint response_length:5;
- GLuint msg_length:4;
- GLuint pad1:2;
- GLuint end_of_thread:1;
+ unsigned function:4;
+ unsigned int_type:1;
+ unsigned precision:1;
+ unsigned saturate:1;
+ unsigned data_type:1;
+ unsigned snapshot:1;
+ unsigned pad0:10;
+ unsigned header_present:1;
+ unsigned response_length:5;
+ unsigned msg_length:4;
+ unsigned pad1:2;
+ unsigned end_of_thread:1;
} math_gen5;
/** G45 PRM, Volume 4, Section 4.8.1.1.1 [DevBW] and [DevCL] */
struct {
- GLuint binding_table_index:8;
- GLuint sampler:4;
- GLuint return_format:2;
- GLuint msg_type:2;
- GLuint response_length:4;
- GLuint msg_length:4;
- GLuint msg_target:4;
- GLuint pad1:3;
- GLuint end_of_thread:1;
+ unsigned binding_table_index:8;
+ unsigned sampler:4;
+ unsigned return_format:2;
+ unsigned msg_type:2;
+ unsigned response_length:4;
+ unsigned msg_length:4;
+ unsigned msg_target:4;
+ unsigned pad1:3;
+ unsigned end_of_thread:1;
} sampler;
/** G45 PRM, Volume 4, Section 4.8.1.1.2 [DevCTG] */
struct {
- GLuint binding_table_index:8;
- GLuint sampler:4;
- GLuint msg_type:4;
- GLuint response_length:4;
- GLuint msg_length:4;
- GLuint msg_target:4;
- GLuint pad1:3;
- GLuint end_of_thread:1;
+ unsigned binding_table_index:8;
+ unsigned sampler:4;
+ unsigned msg_type:4;
+ unsigned response_length:4;
+ unsigned msg_length:4;
+ unsigned msg_target:4;
+ unsigned pad1:3;
+ unsigned end_of_thread:1;
} sampler_g4x;
/** Ironlake PRM, Volume 4 Part 1, Section 4.11.1.1.3 */
struct {
- GLuint binding_table_index:8;
- GLuint sampler:4;
- GLuint msg_type:4;
- GLuint simd_mode:2;
- GLuint pad0:1;
- GLuint header_present:1;
- GLuint response_length:5;
- GLuint msg_length:4;
- GLuint pad1:2;
- GLuint end_of_thread:1;
+ unsigned binding_table_index:8;
+ unsigned sampler:4;
+ unsigned msg_type:4;
+ unsigned simd_mode:2;
+ unsigned pad0:1;
+ unsigned header_present:1;
+ unsigned response_length:5;
+ unsigned msg_length:4;
+ unsigned pad1:2;
+ unsigned end_of_thread:1;
} sampler_gen5;
struct {
- GLuint binding_table_index:8;
- GLuint sampler:4;
- GLuint msg_type:5;
- GLuint simd_mode:2;
- GLuint header_present:1;
- GLuint response_length:5;
- GLuint msg_length:4;
- GLuint pad1:2;
- GLuint end_of_thread:1;
+ unsigned binding_table_index:8;
+ unsigned sampler:4;
+ unsigned msg_type:5;
+ unsigned simd_mode:2;
+ unsigned header_present:1;
+ unsigned response_length:5;
+ unsigned msg_length:4;
+ unsigned pad1:2;
+ unsigned end_of_thread:1;
} sampler_gen7;
struct brw_urb_immediate urb;
struct {
- GLuint opcode:4;
- GLuint offset:6;
- GLuint swizzle_control:2;
- GLuint pad:1;
- GLuint allocate:1;
- GLuint used:1;
- GLuint complete:1;
- GLuint pad0:3;
- GLuint header_present:1;
- GLuint response_length:5;
- GLuint msg_length:4;
- GLuint pad1:2;
- GLuint end_of_thread:1;
+ unsigned opcode:4;
+ unsigned offset:6;
+ unsigned swizzle_control:2;
+ unsigned pad:1;
+ unsigned allocate:1;
+ unsigned used:1;
+ unsigned complete:1;
+ unsigned pad0:3;
+ unsigned header_present:1;
+ unsigned response_length:5;
+ unsigned msg_length:4;
+ unsigned pad1:2;
+ unsigned end_of_thread:1;
} urb_gen5;
struct {
- GLuint opcode:3;
- GLuint offset:11;
- GLuint swizzle_control:1;
- GLuint complete:1;
- GLuint per_slot_offset:1;
- GLuint pad0:2;
- GLuint header_present:1;
- GLuint response_length:5;
- GLuint msg_length:4;
- GLuint pad1:2;
- GLuint end_of_thread:1;
+ unsigned opcode:3;
+ unsigned offset:11;
+ unsigned swizzle_control:1;
+ unsigned complete:1;
+ unsigned per_slot_offset:1;
+ unsigned pad0:2;
+ unsigned header_present:1;
+ unsigned response_length:5;
+ unsigned msg_length:4;
+ unsigned pad1:2;
+ unsigned end_of_thread:1;
} urb_gen7;
struct {
- GLuint binding_table_index:8;
- GLuint search_path_index:3;
- GLuint lut_subindex:2;
- GLuint message_type:2;
- GLuint pad0:4;
- GLuint header_present:1;
+ unsigned binding_table_index:8;
+ unsigned search_path_index:3;
+ unsigned lut_subindex:2;
+ unsigned message_type:2;
+ unsigned pad0:4;
+ unsigned header_present:1;
} vme_gen6;
struct {
- GLuint binding_table_index:8;
- GLuint pad0:5;
- GLuint message_type:2;
- GLuint pad1:4;
- GLuint header_present:1;
+ unsigned binding_table_index:8;
+ unsigned pad0:5;
+ unsigned message_type:2;
+ unsigned pad1:4;
+ unsigned header_present:1;
} cre_gen75;
/** 965 PRM, Volume 4, Section 5.10.1.1: Message Descriptor */
struct {
- GLuint binding_table_index:8;
- GLuint msg_control:4;
- GLuint msg_type:2;
- GLuint target_cache:2;
- GLuint response_length:4;
- GLuint msg_length:4;
- GLuint msg_target:4;
- GLuint pad1:3;
- GLuint end_of_thread:1;
+ unsigned binding_table_index:8;
+ unsigned msg_control:4;
+ unsigned msg_type:2;
+ unsigned target_cache:2;
+ unsigned response_length:4;
+ unsigned msg_length:4;
+ unsigned msg_target:4;
+ unsigned pad1:3;
+ unsigned end_of_thread:1;
} dp_read;
/** G45 PRM, Volume 4, Section 5.10.1.1.2 */
struct {
- GLuint binding_table_index:8;
- GLuint msg_control:3;
- GLuint msg_type:3;
- GLuint target_cache:2;
- GLuint response_length:4;
- GLuint msg_length:4;
- GLuint msg_target:4;
- GLuint pad1:3;
- GLuint end_of_thread:1;
+ unsigned binding_table_index:8;
+ unsigned msg_control:3;
+ unsigned msg_type:3;
+ unsigned target_cache:2;
+ unsigned response_length:4;
+ unsigned msg_length:4;
+ unsigned msg_target:4;
+ unsigned pad1:3;
+ unsigned end_of_thread:1;
} dp_read_g4x;
/** Ironlake PRM, Volume 4 Part 1, Section 5.10.2.1.2. */
struct {
- GLuint binding_table_index:8;
- GLuint msg_control:4;
- GLuint msg_type:2;
- GLuint target_cache:2;
- GLuint pad0:3;
- GLuint header_present:1;
- GLuint response_length:5;
- GLuint msg_length:4;
- GLuint pad1:2;
- GLuint end_of_thread:1;
+ unsigned binding_table_index:8;
+ unsigned msg_control:4;
+ unsigned msg_type:2;
+ unsigned target_cache:2;
+ unsigned pad0:3;
+ unsigned header_present:1;
+ unsigned response_length:5;
+ unsigned msg_length:4;
+ unsigned pad1:2;
+ unsigned end_of_thread:1;
} dp_read_gen5;
/** G45 PRM, Volume 4, Section 5.10.1.1.2. For both Gen4 and G45. */
struct {
- GLuint binding_table_index:8;
- GLuint msg_control:3;
- GLuint last_render_target:1;
- GLuint msg_type:3;
- GLuint send_commit_msg:1;
- GLuint response_length:4;
- GLuint msg_length:4;
- GLuint msg_target:4;
- GLuint pad1:3;
- GLuint end_of_thread:1;
+ unsigned binding_table_index:8;
+ unsigned msg_control:3;
+ unsigned last_render_target:1;
+ unsigned msg_type:3;
+ unsigned send_commit_msg:1;
+ unsigned response_length:4;
+ unsigned msg_length:4;
+ unsigned msg_target:4;
+ unsigned pad1:3;
+ unsigned end_of_thread:1;
} dp_write;
/** Ironlake PRM, Volume 4 Part 1, Section 5.10.2.1.2. */
struct {
- GLuint binding_table_index:8;
- GLuint msg_control:3;
- GLuint last_render_target:1;
- GLuint msg_type:3;
- GLuint send_commit_msg:1;
- GLuint pad0:3;
- GLuint header_present:1;
- GLuint response_length:5;
- GLuint msg_length:4;
- GLuint pad1:2;
- GLuint end_of_thread:1;
+ unsigned binding_table_index:8;
+ unsigned msg_control:3;
+ unsigned last_render_target:1;
+ unsigned msg_type:3;
+ unsigned send_commit_msg:1;
+ unsigned pad0:3;
+ unsigned header_present:1;
+ unsigned response_length:5;
+ unsigned msg_length:4;
+ unsigned pad1:2;
+ unsigned end_of_thread:1;
} dp_write_gen5;
/**
@@ -1401,15 +1395,15 @@ struct brw_instruction
* See the Sandybridge PRM, Volume 4 Part 1, Section 3.9.2.1.1.
**/
struct {
- GLuint binding_table_index:8;
- GLuint msg_control:5;
- GLuint msg_type:3;
- GLuint pad0:3;
- GLuint header_present:1;
- GLuint response_length:5;
- GLuint msg_length:4;
- GLuint pad1:2;
- GLuint end_of_thread:1;
+ unsigned binding_table_index:8;
+ unsigned msg_control:5;
+ unsigned msg_type:3;
+ unsigned pad0:3;
+ unsigned header_present:1;
+ unsigned response_length:5;
+ unsigned msg_length:4;
+ unsigned pad1:2;
+ unsigned end_of_thread:1;
} gen6_dp_sampler_const_cache;
/**
@@ -1423,16 +1417,16 @@ struct brw_instruction
* Section 3.9.9.2.1 of the same volume.
*/
struct {
- GLuint binding_table_index:8;
- GLuint msg_control:5;
- GLuint msg_type:4;
- GLuint send_commit_msg:1;
- GLuint pad0:1;
- GLuint header_present:1;
- GLuint response_length:5;
- GLuint msg_length:4;
- GLuint pad1:2;
- GLuint end_of_thread:1;
+ unsigned binding_table_index:8;
+ unsigned msg_control:5;
+ unsigned msg_type:4;
+ unsigned send_commit_msg:1;
+ unsigned pad0:1;
+ unsigned header_present:1;
+ unsigned response_length:5;
+ unsigned msg_length:4;
+ unsigned pad1:2;
+ unsigned end_of_thread:1;
} gen6_dp;
/**
@@ -1444,31 +1438,31 @@ struct brw_instruction
* control for Render Target Writes.
*/
struct {
- GLuint binding_table_index:8;
- GLuint msg_control:6;
- GLuint msg_type:4;
- GLuint category:1;
- GLuint header_present:1;
- GLuint response_length:5;
- GLuint msg_length:4;
- GLuint pad2:2;
- GLuint end_of_thread:1;
+ unsigned binding_table_index:8;
+ unsigned msg_control:6;
+ unsigned msg_type:4;
+ unsigned category:1;
+ unsigned header_present:1;
+ unsigned response_length:5;
+ unsigned msg_length:4;
+ unsigned pad2:2;
+ unsigned end_of_thread:1;
} gen7_dp;
/** @} */
struct {
- GLuint src1_subreg_nr_high:1;
- GLuint src1_reg_nr:8;
- GLuint pad0:1;
- GLuint src2_rep_ctrl:1;
- GLuint src2_swizzle:8;
- GLuint src2_subreg_nr:3;
- GLuint src2_reg_nr:8;
- GLuint pad1:2;
+ unsigned src1_subreg_nr_high:1;
+ unsigned src1_reg_nr:8;
+ unsigned pad0:1;
+ unsigned src2_rep_ctrl:1;
+ unsigned src2_swizzle:8;
+ unsigned src2_subreg_nr:3;
+ unsigned src2_reg_nr:8;
+ unsigned pad1:2;
} da3src;
- GLint d;
- GLuint ud;
+ int d;
+ unsigned ud;
float f;
} bits3;
};
diff --git a/assembler/gen4asm.h b/assembler/gen4asm.h
index a708c52..8bfbcfe 100644
--- a/assembler/gen4asm.h
+++ b/assembler/gen4asm.h
@@ -35,12 +35,6 @@
#include "brw_reg.h"
-typedef unsigned char GLubyte;
-typedef short GLshort;
-typedef unsigned int GLuint;
-typedef int GLint;
-typedef float GLfloat;
-
extern long int gen_level;
extern int advanced_flag;
extern int errors;
@@ -147,7 +141,7 @@ struct label_instruction {
struct relocation {
char *first_reloc_target, *second_reloc_target; // JIP and UIP respectively
- GLint first_reloc_offset, second_reloc_offset; // in number of instructions
+ int first_reloc_offset, second_reloc_offset; // in number of instructions
};
/**
diff --git a/assembler/gram.y b/assembler/gram.y
index 9d58fe6..50d71d1 100644
--- a/assembler/gram.y
+++ b/assembler/gram.y
@@ -81,7 +81,7 @@ static struct src_operand ip_src =
.reg.dw1.bits.swizzle = BRW_SWIZZLE_NOOP,
};
-static int get_type_size(GLuint type);
+static int get_type_size(unsigned type);
static void set_instruction_opcode(struct brw_program_instruction *instr,
unsigned opcode);
static int set_instruction_dest(struct brw_program_instruction *instr,
@@ -339,7 +339,7 @@ static bool validate_src_reg(struct brw_instruction *insn,
return true;
}
-static int get_subreg_address(GLuint regfile, GLuint type, GLuint subreg, GLuint address_mode)
+static int get_subreg_address(unsigned regfile, unsigned type, unsigned subreg, unsigned address_mode)
{
int unit_size = 1;
@@ -370,7 +370,7 @@ static int get_subreg_address(GLuint regfile, GLuint type, GLuint subreg, GLuint
* a0.12 6 invalid input
* a0.14 7 invalid input
*/
-static int get_indirect_subreg_address(GLuint subreg)
+static int get_indirect_subreg_address(unsigned subreg)
{
return advanced_flag == 0 ? subreg / 2 : subreg;
}
@@ -2744,7 +2744,7 @@ void yyerror (char *msg)
++errors;
}
-static int get_type_size(GLuint type)
+static int get_type_size(unsigned type)
{
int size = 1;
--
1.7.7.5
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