[Intel-gfx] [PATCH 08/15] drm/i915: WARN if IIR is not zero at irq_postinstall

[Paulo Zanoni]

From: Paulo Zanoni <paulo.r.zanoni at intel.com>

Because now we're clearing the IIR register at preinstall and
uninstall, so let's just check if it's still zero at postinstall.
Since we should be disabling the interrupts at preinstall, there is no
way the IIR could become non-zero at postinstall, so this patch may
uncover bugs (e.g., missing code at preinstall).

Signed-off-by: Paulo Zanoni <paulo.r.zanoni at intel.com>
---
 drivers/gpu/drm/i915/i915_irq.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 400aa63..6793b30 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -90,8 +90,7 @@ static const u32 hpd_status_i915[] = { /* i915 and valleyview are the same */
 } while (0)
 
 #define INTEL_IRQ_REG_INIT(type, do_iir, ier_val, imr_val) do { \
-	if (do_iir) \
-		I915_WRITE(type##IR, I915_READ(type##IR)); \
+	WARN(I915_READ(type##IR) != 0, "Register 0x%x is not 0\n", type##IR); \
 	I915_WRITE(type##MR, (imr_val)); \
 	I915_WRITE(type##ER, (ier_val)); \
 	POSTING_READ(type##ER); \
-- 
1.8.1.2