[Intel-gfx] [PATCH 1/2] drm/i915: fixed EDID/sink-based bpp clamping

[Daniel Vetter]

On Sat, Jun 01, 2013 at 06:52:39PM +0100, Chris Wilson wrote:
> On Sat, Jun 01, 2013 at 07:45:55PM +0200, Daniel Vetter wrote:
> > Since this is run in the compute config stage we need to check
> > the new_ pointers, not the current modeset layout. Also there
> > was a little logic bug in properly skipping connectors. This has
> > been broken when moving the pipe bpp selection in
> > 
> > commit 4e53c2e010e531b4a014692199e978482d471c7e
> > Author: Daniel Vetter <daniel.vetter at ffwll.ch>
> > Date:   Wed Mar 27 00:44:58 2013 +0100
> > 
> >     drm/i915: precompute pipe bpp before touching the hw
> > 
> > To avoid too much casting switch from drm_ to intel_ types.
> > 
> > Also add a bit of debug output to help reconstructing what's going
> > on.
> 
> Baffling. It is really hard to tell what is going on, so perhaps it is
> worth investing in some more descriptive names. How about:
>   struct drm_display_info *desired = &connector->base.display_info ?
> Or some other name? And an indication in the function name at which
> stage this is meant to run?

I guess renaming the function to pipe_config_compute_bpp would help (since
it doesn't really set anything). And maybe extracting the sink based bpp
limiting into it's own function since it's a bit magic.

I'll see whether I can polish this turd some more.
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch