[Intel-gfx] [PATCH 5/6] drm/i915: initialize the PCH GTC interrupts

[Paulo Zanoni]

From: Paulo Zanoni <paulo.r.zanoni at intel.com>

These regsiters only exist on LPT and we still don't use them.
Initialize them for the same reason as we initialize the other
interrupts we don't use (SRD, FDI_RX, AUD).

Notice that we also have CPU GTC registers, but these registers are
disabled when the power well is disabled, so they must be handled
differently. Also, they don't affect the code for package C8+ since
we need the power well disabled to enter PC8+.

Signed-off-by: Paulo Zanoni <paulo.r.zanoni at intel.com>
---
 drivers/gpu/drm/i915/i915_irq.c | 15 +++++++++++++++
 drivers/gpu/drm/i915/i915_reg.h |  3 +++
 2 files changed, 18 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index c21055e..dc2658c 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2498,6 +2498,11 @@ static void ibx_irq_preinstall(struct drm_device *dev)
 		if (HAS_PCH_LPT(dev))
 			break;
 	}
+
+	if (HAS_PCH_LPT(dev)) {
+		I915_WRITE(PCH_GTCIMR, 0xffffffff);
+		POSTING_READ(PCH_GTCIMR);
+	}
 }
 
 /* drm_dma.h hooks
@@ -2657,6 +2662,11 @@ static void ibx_irq_postinstall(struct drm_device *dev)
 		if (HAS_PCH_LPT(dev))
 			break;
 	}
+
+	if (HAS_PCH_LPT(dev)) {
+		I915_WRITE(PCH_GTCIMR, 0xffffffff);
+		I915_WRITE(PCH_GTCIIR, I915_READ(PCH_GTCIIR));
+	}
 }
 
 static int ironlake_irq_postinstall(struct drm_device *dev)
@@ -2899,6 +2909,11 @@ static void ironlake_irq_uninstall(struct drm_device *dev)
 		if (HAS_PCH_LPT(dev))
 			break;
 	}
+
+	if (HAS_PCH_LPT(dev)) {
+		I915_WRITE(PCH_GTCIMR, 0xffffffff);
+		I915_WRITE(PCH_GTCIIR, I915_READ(PCH_GTCIIR));
+	}
 }
 
 static void i8xx_irq_preinstall(struct drm_device * dev)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index f996e9f..6a977ce 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3740,6 +3740,9 @@
 #define SRDIMR	0x64834
 #define SRDIIR	0x64838
 
+#define PCH_GTCIMR	0xe7054
+#define PCH_GTCIIR	0xe7058
+
 #define ILK_DISPLAY_CHICKEN2	0x42004
 /* Required on all Ironlake and Sandybridge according to the B-Spec. */
 #define  ILK_ELPIN_409_SELECT	(1 << 25)
-- 
1.8.1.2