[Intel-gfx] [PATCH 6/6] drm/i915: More HSW PM clean up.

[Chris Wilson]

On Fri, Mar 22, 2013 at 06:13:50PM -0300, Rodrigo Vivi wrote:
> 
> 
> 
> On Wed, Feb 27, 2013 at 10:46 AM, Paulo Zanoni <przanoni at gmail.com> wrote:
>      Hi
> 
>      2013/2/25 Rodrigo Vivi <rodrigo.vivi at gmail.com>:
>      > This is the last cleaning up patch for HSW, letting render standby
>      > programming sequence like the documented one at HSW PM programing
>      guide.
>      >
>      > Signed-off-by: Rodrigo Vivi <rodrigo.vivi at gmail.com>
>      > ---
>      >  drivers/gpu/drm/i915/intel_pm.c | 9 ---------
>      >  1 file changed, 9 deletions(-)
>      >
>      > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/
>      i915/intel_pm.c
>      > index d43e011..ef51174 100644
>      > --- a/drivers/gpu/drm/i915/intel_pm.c
>      > +++ b/drivers/gpu/drm/i915/intel_pm.c
>      > @@ -2749,16 +2749,7 @@ static void hsw_enable_rps(struct drm_device
>      *dev)
>      >                    GEN6_RP_UP_BUSY_AVG |
>      >                    GEN7_RP_DOWN_IDLE_AVG);
>      >
>      > -       gen6_set_rps(dev_priv->dev, (gt_perf_status & 0xff00)
>      >> 8);
> 
>      Looks like the line above is not even on the SNB docs, and git blame
>      shows it's a bug fix. I'll let Chris comment on that. Having a nice
>      comment explaining why that code is there would be good :)
> 
> Any comment Chris? what is this for? is this still needed for HSW?

Yes, it is still needed for our keeping our RPS state tracking in sync
with the register values.
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre