[Intel-gfx] [PATCH] drm/i915: Apply alignment restrictions on scanout surfaces for VT-d

[Damien Lespiau]

On Tue, Mar 05, 2013 at 02:52:39PM +0000, Chris Wilson wrote:
> From the w/a database:
> 
> 'To prevent false VT-d type 6 error:
> 
>   The primary display plane must be 256KiB aligned, and require an extra
>   128 PTEs of padding afterward;
> 
>   The sprites planes must be 128KiB aligned, and require an extra 64 PTEs
>   of padding afterward;
> 
>   The cursors must be 64KiB aligned, and require an extra 2 PTEs of
>   padding afterward.'
> 
> As we use the same function to pin the primary and sprite planes, we can
> simply use the more strict requirements for scanouts for both.
> 
> Instead of using explicit padding PTEs following the scanout objects, we
> should be able to use the scratch page that is always mapped into the
> unused PTEs to avoid the VT-d error.
> 
> References: https://bugs.freedesktop.org/show_bug.cgi?id=59626
> References: https://bugs.freedesktop.org/show_bug.cgi?id=59627
> References: https://bugs.freedesktop.org/show_bug.cgi?id=59631
> Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>

Reviewed-by: Damien Lespiau <damien.lespiau at intel.com>

Maybe rename the mentions to "shadow page" to scratch page as it's the
name used elsewhere. I also like the even more explicit function name
from Daniel. In any case, sounds like a good patch to have.

-- 
Damien