[Intel-gfx] [PATCH] drm/i915/hsw: Disable L3 caching of atomic memory operations.

Daniel Vetter daniel at ffwll.ch
Thu Oct 3 00:20:43 CEST 2013

On Thu, Oct 3, 2013 at 12:03 AM, Francisco Jerez <currojerez at riseup.net> wrote:
> +       case I915_PARAM_HAS_ATOMICS:
> +               value = 1;
> +               break;

Generally when we do kernel fixes for gpu hangs like that we don't add
parameters (would drown in them otherwise) but simply queue it up to
-fixes and slap a cc: stable on it. Gpu hang fixes are critical enough
imo for that treatment, even when it's for brand new userspace code.

Any specific reason why we shouldn't follow this approach here? I'd
make the patch simpler and we could dump a bit of userspace code, too.
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

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