[Intel-gfx] [PATCH] drm/i915/hsw: Disable L3 caching of atomic memory operations.
currojerez at riseup.net
Thu Oct 3 00:31:40 CEST 2013
Daniel Vetter <daniel at ffwll.ch> writes:
> On Thu, Oct 3, 2013 at 12:03 AM, Francisco Jerez <currojerez at riseup.net> wrote:
>> + case I915_PARAM_HAS_ATOMICS:
>> + value = 1;
>> + break;
> Generally when we do kernel fixes for gpu hangs like that we don't add
> parameters (would drown in them otherwise) but simply queue it up to
> -fixes and slap a cc: stable on it. Gpu hang fixes are critical enough
> imo for that treatment, even when it's for brand new userspace code.
> Any specific reason why we shouldn't follow this approach here? I'd
> make the patch simpler and we could dump a bit of userspace code, too.
Not really, I'm fine either way. I'll send a revised version of this
patch without the param change.
> Daniel Vetter
> Software Engineer, Intel Corporation
> +41 (0) 79 365 57 48 - http://blog.ffwll.ch
-------------- next part --------------
A non-text attachment was scrubbed...
Name: not available
Size: 229 bytes
Desc: not available
More information about the Intel-gfx