[Intel-gfx] Questions on display pipes on 835GM
thor at math.tu-berlin.de
Sun Oct 6 01:09:49 CEST 2013
> btw I've just read through your dvo code again and I think we can fix this
> easier. If I read your enable hack correctly then we need to have the dpll
> running and the DVO port on. The problem now is that in the dvo ->modeset
> callback this is explicitly _not_ the case.
Please also check the latest mail (just minutes above). There seem to be
three conditions, actually: DPLL running, DVO on, and high-speed mode
selected *at least* if there is only one pipe active.
> This is not a big issue when there's only one pipe in use, but it wreaks
> havoc when more than one pipe is in use. So we need to move all that code
> somewhere else.
> Now if you follow the callchains around the dvo->dpms callbacks the DVO
> port and DPLL are always enabled at that point in time, so I think we
> should be able to fix this all by moving the modeset code around to that
True, but probably with the high-speed bit in the wrong state.
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