[Intel-gfx] Questions on display pipes on 835GM

Daniel Vetter daniel at ffwll.ch
Sun Oct 6 01:37:46 CEST 2013

On Sun, Oct 6, 2013 at 1:09 AM, Thomas Richter <thor at math.tu-berlin.de> wrote:
>> Now if you follow the callchains around the dvo->dpms callbacks the DVO
>> port and DPLL are always enabled at that point in time, so I think we
>> should be able to fix this all by moving the modeset code around to that
>> place.
> True, but probably with the high-speed bit in the wrong state.

We always program the dpll with the high-speed select bit set when
using it for a DVO port, so this will also automatically be taken care
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

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