[Intel-gfx] [PATCH 2/4] drm/i915: Remove WaFbcDisableDpfcClockGating on HSW

Ben Widawsky ben at bwidawsk.net
Mon Oct 28 21:24:29 CET 2013


On Mon, Oct 28, 2013 at 07:43:30PM +0200, Ville Syrjälä wrote:
> On Mon, Oct 28, 2013 at 09:48:55AM -0700, Ben Widawsky wrote:
> > On Mon, Oct 28, 2013 at 03:05:12PM +0200, Ville Syrjälä wrote:
> > > On Mon, Oct 28, 2013 at 10:22:31AM -0200, Paulo Zanoni wrote:
> > > > 2013/10/27 Daniel Vetter <daniel at ffwll.ch>:
> > > > > On Fri, Oct 25, 2013 at 03:27:50PM -0200, Paulo Zanoni wrote:
> > > > >> 2013/10/24 Ben Widawsky <benjamin.widawsky at intel.com>:
> > > > >> > Production HSW does not need it. I confirmed this with Art.
> > > > >> >
> > > > >> > Signed-off-by: Ben Widawsky <ben at bwidawsk.net>
> > > > >>
> > > > >> I just hope these things don't start uncovering bugs :)
> > > > >>
> > > > >> Reviewed-by: Paulo Zanoni <paulo.r.zanoni at intel.com>
> > > > >
> > > > > Merged the first 2 patches of this series. Not sure what to do with the
> > > > > other two, since fbc is essentially disabled on pre-hsw. And no one seems
> > > > > to really work on it :( So I only see minimal reasons to frob with it ...
> > > > 
> > > > IMHO what you said is another reason to actually merge the other two
> > > > patches, since they make FBC-only WAs be applied only on FBC (e.g.,
> > > > probably never).
> > > 
> > > Another reason would be keeping the codepaths at least somewhat similar.
> > > Could make it a bit easier to fix things later. If it would be me who
> > > gets to fix the FBC mess at some point, I'd try to fix it for all gens
> > > for sure.
> > > 
> > > At some point I posted a patch to attempt a quick FBC fix for SNB:
> > > "[PATCH] drm/i915: Attempt to fix FBC render tracking with hardware contexts"
> > > 
> > > In theory that could make FBC work equally well for SNB as it works for
> > > IVB+. And I must confess that I have FBC enabled on my IVB ultrabook
> > > currently since it appears to save a rather significant amount of power.
> > > 
> > > -- 
> > > Ville Syrjälä
> > > Intel OTC
> > 
> > 
> > I just looked at your patch, and I should probably comment there, but
> > it's 5 months old :D. Did you actually observe a fix of something with
> > that patch? I feel like the way in which we enable/disable tracking, it
> > shouldn't make a difference.
> 
> I've never even tried to enable FBC on SNB ;)
> 
> But it should easy to trick it into doing the wrong thing.
> 
> 1) switch to context A
> 2) page flip to buf 0 
>    -> FBC RT address will point to buf 0
> 3) switch to context B
> 4) page flip to buf 1
>    -> FBC RT address will point to buf 1
> 5) switch to context A
>    -> FBC RT addres will be restored to point to buf 0
> 6) render into buf 1 and observe that FBC doesn't invalidate
>    the compressed data
> 
> -- 
> Ville Syrjälä
> Intel OTC

I thought this is fine because we set the enable bit concurrently with
the base address, and disable when not being used. I really don't know
the code well enough though.

-- 
Ben Widawsky, Intel Open Source Technology Center



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