[Intel-gfx] [PATCH v2 3/6] drm/i915: Enabling the TLB invalidate bit in GFX Mode register

[Daniel Vetter]

On Wed, Apr 02, 2014 at 02:34:59PM +0300, Ville Syrjälä wrote:
> On Mon, Mar 24, 2014 at 11:00:04PM +0530, sourab.gupta at intel.com wrote:
> > From: Akash Goel <akash.goel at intel.com>
> > 
> > This patch Enables the bit for TLB invalidate in GFX Mode register
> > for Gen7.
> > 
> > According to bspec,  When enabled this bit limits the invalidation
> > of the TLB only to batch buffer boundaries, to pipe_control
> > commands which have the TLB invalidation bit set and sync flushes.
> > If disabled, the TLB caches are flushed for every full flush of
> > the pipeline.
> > 
> > Tested only on vlv platform. Chris has tested on ivb and hsw
> > platforms.
> > 
> > v2: Adding the explicit enabling of this bit for all Gen7 platforms
> > instead of only vlv (Chris)
> > 
> > Signed-off-by: Akash Goel <akash.goel at intel.com>
> > Signed-off-by: Sourab Gupta <sourab.gupta at intel.com>
> > Tested-by: Chris Wilson <chris at chris-wilson.co.uk> #ivb, hsw -Chris
> 
> Could I trouble you to add the w/a note?
> WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw
> 
> No idea why it mentions only BCS and VCS, but it does seem to say that
> it's essentially a new name for WaEnableFlushTlbInvalidationMode:snb.

Done for both the gen6 and gen7 version of this.
> 
> With that:
> Reviewed-by: Ville Syrjälä <ville.syrjala at linux.intel.com>

Signed-off-by: Daniel Vetter <daniel.vetter at ffwll.ch>
> 
> > ---
> >  drivers/gpu/drm/i915/intel_ringbuffer.c | 2 +-
> >  1 file changed, 1 insertion(+), 1 deletion(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> > index bace089..eb4811a 100644
> > --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> > +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> > @@ -617,7 +617,7 @@ static int init_render_ring(struct intel_ring_buffer *ring)
> >  
> >  	if (IS_GEN7(dev))
> >  		I915_WRITE(GFX_MODE_GEN7,
> > -			   _MASKED_BIT_DISABLE(GFX_TLB_INVALIDATE_EXPLICIT) |
> > +			   _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT) |
> >  			   _MASKED_BIT_ENABLE(GFX_REPLAY_MODE));
> >  
> >  	if (INTEL_INFO(dev)->gen >= 5) {
> > -- 
> > 1.8.5.1
> 
> -- 
> Ville Syrjälä
> Intel OTC

-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch