[Intel-gfx] [PATCH 1/6] drm/i915: Replace hardcoded cacheline size with macro

[Jesse Barnes]

On Wed,  2 Apr 2014 16:36:06 +0100
Chris Wilson <chris at chris-wilson.co.uk> wrote:

> For readibility and guess at the meaning behind the constants.
> 
> Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
> ---
>  drivers/gpu/drm/i915/intel_ringbuffer.c | 29 ++++++++++++++++-------------
>  1 file changed, 16 insertions(+), 13 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index 785f246d28a8..475391ce671a 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -33,6 +33,8 @@
>  #include "i915_trace.h"
>  #include "intel_drv.h"
>  
> +#define CACHELINE_BYTES 64
> +

Are you sure it's 64 on every gen?  It changes on the CPU side from
time to time... I thought it might have changed over time on the GPU
too but I haven't checked the specs.

Either way a doc ref would be nice here.

-- 
Jesse Barnes, Intel Open Source Technology Center