[Intel-gfx] [PATCH 1/6] drm/i915: Replace hardcoded cacheline size with macro

[Chris Wilson]

On Wed, Apr 02, 2014 at 02:57:11PM -0700, Jesse Barnes wrote:
> On Wed,  2 Apr 2014 16:36:06 +0100
> Chris Wilson <chris at chris-wilson.co.uk> wrote:
> 
> > For readibility and guess at the meaning behind the constants.
> > 
> > Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
> > ---
> >  drivers/gpu/drm/i915/intel_ringbuffer.c | 29 ++++++++++++++++-------------
> >  1 file changed, 16 insertions(+), 13 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> > index 785f246d28a8..475391ce671a 100644
> > --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> > +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> > @@ -33,6 +33,8 @@
> >  #include "i915_trace.h"
> >  #include "intel_drv.h"
> >  
> > +#define CACHELINE_BYTES 64
> > +
> 
> Are you sure it's 64 on every gen?  It changes on the CPU side from
> time to time... I thought it might have changed over time on the GPU
> too but I haven't checked the specs.

The cacheline is 32bytes on gen2, 64 elsewhere. We've made a blanket
assumption of 64 and then some random factors on top. (Some cachelines
may be as large as 1024bytes elsewhere in the chip.) I'm not sure where
some of the values used in the code where plucked from, Jesse?
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre