[Intel-gfx] [PATCH 1/3] drm/i915: consider the source max DP lane count too

[Jani Nikula]

On Fri, 25 Apr 2014, Paulo Zanoni <przanoni at gmail.com> wrote:
> From: Paulo Zanoni <paulo.r.zanoni at intel.com>
>
> Even if the panel claims it can support 4 lanes, there's the
> possibility that the HW can't, so consider this while selecting the
> max lane count.
>
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni at intel.com>
> ---
>  drivers/gpu/drm/i915/intel_dp.c | 20 ++++++++++++++++++--
>  1 file changed, 18 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 104998e..19537a6 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -120,6 +120,22 @@ intel_dp_max_link_bw(struct intel_dp *intel_dp)
>  	return max_link_bw;
>  }
>  
> +static u8 intel_dp_max_lane_count(struct intel_dp *intel_dp)
> +{
> +	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
> +	struct drm_device *dev = intel_dig_port->base.base.dev;
> +	u8 source_max, sink_max;
> +
> +	source_max = 4;
> +	if (HAS_DDI(dev) && intel_dig_port->port == PORT_A &&
> +	    (intel_dig_port->saved_port_bits & DDI_A_4_LANES) == 0)
> +		source_max = 2;

Wow, good catch. Are you aware of similar restrictions on other
platforms?

Does this potentially fix
https://bugs.freedesktop.org/show_bug.cgi?id=73539 ?

BR,
Jani.

> +
> +	sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
> +
> +	return min(source_max, sink_max);
> +}
> +
>  /*
>   * The units on the numbers in the next two are... bizarre.  Examples will
>   * make it clearer; this one parallels an example in the eDP spec.
> @@ -170,7 +186,7 @@ intel_dp_mode_valid(struct drm_connector *connector,
>  	}
>  
>  	max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
> -	max_lanes = drm_dp_max_lane_count(intel_dp->dpcd);
> +	max_lanes = intel_dp_max_lane_count(intel_dp);
>  
>  	max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
>  	mode_rate = intel_dp_link_required(target_clock, 18);
> @@ -764,7 +780,7 @@ intel_dp_compute_config(struct intel_encoder *encoder,
>  	struct intel_crtc *intel_crtc = encoder->new_crtc;
>  	struct intel_connector *intel_connector = intel_dp->attached_connector;
>  	int lane_count, clock;
> -	int max_lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
> +	int max_lane_count = intel_dp_max_lane_count(intel_dp);
>  	/* Conveniently, the link BW constants become indices with a shift...*/
>  	int max_clock = intel_dp_max_link_bw(intel_dp) >> 3;
>  	int bpp, mode_rate;
> -- 
> 1.9.0
>
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-- 
Jani Nikula, Intel Open Source Technology Center