[Intel-gfx] [PATCH 3/3] drm/i915: add i915.dp_link_train_policy option
Barbalho, Rafael
rafael.barbalho at intel.com
Fri Apr 25 12:48:44 CEST 2014
<snip>
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni at intel.com>
> ---
> drivers/gpu/drm/i915/i915_drv.h | 1 +
> drivers/gpu/drm/i915/i915_params.c | 8 ++++++++
> drivers/gpu/drm/i915/intel_dp.c | 39
> ++++++++++++++++++++++++++++++++++----
> 3 files changed, 44 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h
> b/drivers/gpu/drm/i915/i915_drv.h index 7d6acb4..d5ae8dc 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1941,6 +1941,7 @@ struct i915_params {
> bool reset;
> bool disable_display;
> bool disable_vtd_wa;
> + int dp_link_train_policy;
> };
> extern struct i915_params i915 __read_mostly;
>
> diff --git a/drivers/gpu/drm/i915/i915_params.c
> b/drivers/gpu/drm/i915/i915_params.c
> index d05a2af..8c358e7 100644
> --- a/drivers/gpu/drm/i915/i915_params.c
> +++ b/drivers/gpu/drm/i915/i915_params.c
> @@ -48,6 +48,7 @@ struct i915_params i915 __read_mostly = {
> .disable_display = 0,
> .enable_cmd_parser = 1,
> .disable_vtd_wa = 0,
> + .dp_link_train_policy = 0,
> };
>
> module_param_named(modeset, i915.modeset, int, 0400); @@ -156,3
> +157,10 @@ MODULE_PARM_DESC(disable_vtd_wa, "Disable all VT-d
> workarounds (default: false)"
> module_param_named(enable_cmd_parser, i915.enable_cmd_parser, int,
> 0600); MODULE_PARM_DESC(enable_cmd_parser,
> "Enable command parsing (1=enabled [default],
> 0=disabled)");
> +
> +module_param_named(dp_link_train_policy, i915.dp_link_train_policy,
> +int, 0600); MODULE_PARM_DESC(dp_link_train_policy,
> + "Choose strategy for DP link training "
> + "(0=narrow and fast [default], 1=wide and slow. For other values, "
> + "bits 11:8 are for the BW and bits 7:4 are for the nubmer of lanes, "
> + "check intel_dp_compute_link_config() for more details.)");
There is a typo here, nubmer should be number, otherwise:
Reviewed-by: Rafael Barbalho <rafael.barbalho at intel.com>
More information about the Intel-gfx
mailing list