[Intel-gfx] [PATCH 11/11] drm/i915: gen5+ can have FBC with multiple pipes

[shuang.he at intel.com]

Tested-By: PRC QA PRTS (Patch Regression Test System Contact: shuang.he at intel.com)
-------------------------------------Summary-------------------------------------
Platform          Delta          drm-intel-nightly          Series Applied
PNV                                  364/364              364/364
ILK              +1                 364/366              365/366
SNB                 -1              448/450              447/450
IVB                                  497/498              497/498
BYT                                  289/289              289/289
HSW                                  563/564              563/564
BDW                                  417/417              417/417
-------------------------------------Detailed-------------------------------------
Platform  Test                                drm-intel-nightly          Series Applied
 ILK  igt_kms_flip_wf_vblank-ts-check      DMESG_WARN(1, M26)PASS(5, M26M37)      PASS(1, M37)
*SNB  igt_gem_concurrent_blit_gtt-rcs-early-read-forked      PASS(2, M35M22)      FAIL(1, M22)
Note: You need to pay more attention to line start with '*'