[Intel-gfx] [PATCH 1/3] drm/i915: Invalidate media caches on gen7

[Chris Wilson]

On Mon, Dec 15, 2014 at 10:34:45AM +0100, Daniel Vetter wrote:
> On Thu, Dec 11, 2014 at 08:16:59AM +0000, Chris Wilson wrote:
> > In the gen7 pipe control there is an extra bit to flush the media
> > caches, so let's set it during cache invalidation flushes.
> > 
> > Cc: Simon Farnsworth <simon at farnz.org.uk>
> > Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
> > Cc: stable at vger.kernel.org
> > ---
> >  drivers/gpu/drm/i915/i915_reg.h         | 1 +
> >  drivers/gpu/drm/i915/intel_ringbuffer.c | 1 +
> >  2 files changed, 2 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index 93fdad8a7447..0ddef7256d02 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -400,6 +400,7 @@
> >  #define   PIPE_CONTROL_STORE_DATA_INDEX			(1<<21)
> >  #define   PIPE_CONTROL_CS_STALL				(1<<20)
> >  #define   PIPE_CONTROL_TLB_INVALIDATE			(1<<18)
> > +#define   PIPE_CONTROL_MEDIA_CACHE_INVALIDATE		(1<<16)
> 
> Maybe call it STATE_CLEAR since that's what Bspec calls it. libva doesn't
> use this, so I have no idea what it means. I also wonder whether we should
> nuke indirect state (bit9), too? Just to make sure the context switch
> doesn't fall over between 3d and media pipeline.
> 

I am not sure if we should use "indirect state pointers disable" as that
affects the context image. If userspace is using indirect state pointers
and contexts, it will expect the GPU state to be maintain across the
unforseeable context switches. Userspace would have to zap the pointers
itself if it does not want them preserved.

> Anyway if it helps it must be good. With the rename applied:

I don't have anything to suggest this improved matters, it was just
mentioned in conjunction with context switches in the bspec and seemed
appropriate when thinking about libva...
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre