[Intel-gfx] [PATCH 1/3] drm/i915: Invalidate media caches on gen7

[Daniel Vetter]

On Thu, Dec 11, 2014 at 08:16:59AM +0000, Chris Wilson wrote:
> In the gen7 pipe control there is an extra bit to flush the media
> caches, so let's set it during cache invalidation flushes.
> 
> Cc: Simon Farnsworth <simon at farnz.org.uk>
> Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
> Cc: stable at vger.kernel.org
> ---
>  drivers/gpu/drm/i915/i915_reg.h         | 1 +
>  drivers/gpu/drm/i915/intel_ringbuffer.c | 1 +
>  2 files changed, 2 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 93fdad8a7447..0ddef7256d02 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -400,6 +400,7 @@
>  #define   PIPE_CONTROL_STORE_DATA_INDEX			(1<<21)
>  #define   PIPE_CONTROL_CS_STALL				(1<<20)
>  #define   PIPE_CONTROL_TLB_INVALIDATE			(1<<18)
> +#define   PIPE_CONTROL_MEDIA_CACHE_INVALIDATE		(1<<16)

Maybe call it STATE_CLEAR since that's what Bspec calls it. libva doesn't
use this, so I have no idea what it means. I also wonder whether we should
nuke indirect state (bit9), too? Just to make sure the context switch
doesn't fall over between 3d and media pipeline.

Anyway if it helps it must be good. With the rename applied:

Reviewed-by: Daniel Vetter <daniel.vetter at ffwll.ch>

>  #define   PIPE_CONTROL_QW_WRITE				(1<<14)
>  #define   PIPE_CONTROL_POST_SYNC_OP_MASK                (3<<14)
>  #define   PIPE_CONTROL_DEPTH_STALL			(1<<13)
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index 4702e7bcd71c..282279b83ca4 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -373,6 +373,7 @@ gen7_render_ring_flush(struct intel_engine_cs *ring,
>  		flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
>  		flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
>  		flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
> +		flags |= PIPE_CONTROL_MEDIA_CACHE_INVALIDATE;
>  		/*
>  		 * TLB invalidate requires a post-sync write.
>  		 */
> -- 
> 2.1.3
> 
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-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch