[Intel-gfx] [PATCH 0/2] drm/i915: IVB MI_DISPLAY_FLIP cacheline trick v2

[ville.syrjala at linux.intel.com]

From: Ville Syrjälä <ville.syrjala at linux.intel.com>

BSpec tells us that the entire MI_DISPLAY_FLIP packet must be contained
within a single cacheline on IVB. This series achieves that.

Changes since my original patch [1]:
* Move the logic into a new intel_ring_begin_cacheline_safe() function
  (as suggested by Daniel).
* Actually handle the case when the ring would wrap due to the extra
  dwords. With the original patch, the MI_DISPLAY_FLIP packet might still
  end up straddling two cachelines in this case.

Changes since v1 [2]:
* Just do the simple cacheline alignment trick Chris suggested

[1] https://bugs.freedesktop.org/show_bug.cgi?id=74053#
[2] http://lists.freedesktop.org/archives/intel-gfx/2014-February/039921.html

Ville Syrjälä (2):
  drm/i915: Add intel_ring_cachline_align()
  drm/i915: Prevent MI_DISPLAY_FLIP straddling two cachelines on IVB

 drivers/gpu/drm/i915/intel_display.c    | 14 ++++++++++++++
 drivers/gpu/drm/i915/intel_ringbuffer.c | 21 +++++++++++++++++++++
 drivers/gpu/drm/i915/intel_ringbuffer.h |  1 +
 3 files changed, 36 insertions(+)

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1.8.3.2