[Intel-gfx] [PATCH v3 2/2] drm/i915: Prevent MI_DISPLAY_FLIP straddling two cachelines on IVB

[Chris Wilson]

On Tue, Feb 11, 2014 at 07:52:06PM +0200, ville.syrjala at linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala at linux.intel.com>
> 
> According to BSpec the entire MI_DISPLAY_FLIP packet must be contained
> in a single cacheline. Make sure that happens.
> 
> v2: Use intel_ring_begin_cacheline_safe()
> v3: Use intel_ring_cacheline_align() (Chris)
> 
> Cc: Bjoern C <lkml at call-home.ch>
> Cc: Alexandru DAMIAN <alexandru.damian at intel.com>
> Cc: Enrico Tagliavini <enrico.tagliavini at gmail.com>
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=74053
> Signed-off-by: Ville Syrjälä <ville.syrjala at linux.intel.com>

I would have used intel_ring_align_cacheline() as it seems more natural
for me to say...

Both,
Reviewed-by: Chris Wilson <chris at chris-wilson.co.uk>
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre