[Intel-gfx] [PATCH v3 2/2] drm/i915: Prevent MI_DISPLAY_FLIP straddling two cachelines on IVB

[Ville Syrjälä]

On Tue, Feb 11, 2014 at 08:19:13PM +0000, Chris Wilson wrote:
> On Tue, Feb 11, 2014 at 07:52:06PM +0200, ville.syrjala at linux.intel.com wrote:
> > From: Ville Syrjälä <ville.syrjala at linux.intel.com>
> > 
> > According to BSpec the entire MI_DISPLAY_FLIP packet must be contained
> > in a single cacheline. Make sure that happens.
> > 
> > v2: Use intel_ring_begin_cacheline_safe()
> > v3: Use intel_ring_cacheline_align() (Chris)
> > 
> > Cc: Bjoern C <lkml at call-home.ch>
> > Cc: Alexandru DAMIAN <alexandru.damian at intel.com>
> > Cc: Enrico Tagliavini <enrico.tagliavini at gmail.com>
> > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=74053
> > Signed-off-by: Ville Syrjälä <ville.syrjala at linux.intel.com>
> 
> I would have used intel_ring_align_cacheline() as it seems more natural
> for me to say...

I had it as intel_ring_align_to_cacheline(), but then changed it when I
saw Daniel's suggestion for the name. So you can blame Daniel for this ;)
But I have no emotional attachment to the chosen name. So if you prefer
we rename it, I'm fine with that.

-- 
Ville Syrjälä
Intel OTC