[Intel-gfx] [PATCH] drm/i915: Avoid div by zero when pixel clock is large

[Chris Wilson]

On Fri, Feb 14, 2014 at 02:18:57PM +0200, ville.syrjala at linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala at linux.intel.com>
> 
> Make sure the line_time_us isn't zero in the gmch watermarks code as
> that would cause a div by zero. This can be triggered by specifying
> a very fast pixel clock for the mode.

Very fast but valid? If it was just very fast, we should have rejected
the mode line. On the other hand, if it was valid, maybe we should
adjust the bias (* 1000 / 1000) so that the computation remains
reasonably accurate because we will need a larger FIFO to accommodate
the higher clock rate.

Anyway, even with the larger bias, such a safe guard is sensisble. I
can't argue against this patch, but I just wonder if you opened a can of
worms.
Reviewed-by: Chris Wilson <chris at chris-wilson.co.uk>
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre