[Intel-gfx] [PATCH] drm/i915: Avoid div by zero when pixel clock is large

[Ville Syrjälä]

On Fri, Feb 14, 2014 at 12:28:29PM +0000, Chris Wilson wrote:
> On Fri, Feb 14, 2014 at 02:18:57PM +0200, ville.syrjala at linux.intel.com wrote:
> > From: Ville Syrjälä <ville.syrjala at linux.intel.com>
> > 
> > Make sure the line_time_us isn't zero in the gmch watermarks code as
> > that would cause a div by zero. This can be triggered by specifying
> > a very fast pixel clock for the mode.
> 
> Very fast but valid?

74.25 GHz. I'm not sure which way you would classify that :)

> If it was just very fast, we should have rejected
> the mode line.

Except we do more or less zero checks on the mode supplied to the
setcrtc ioctl. Something we should really get fixed at some point.

-- 
Ville Syrjälä
Intel OTC