[Intel-gfx] [PATCH 00/19] drm/i915: vlv power domains support

[Imre Deak]

This patchset adds support for enabling/disabling dynamic power-wells on
VLV on-demand.

Before enabling on-demand power well toggling the patchset adds the
checks for required power domains for places that poke at the HW. These
are the pipe, encoder and connector HW state readout functions. It also
does a get/put of required power domains in the connector detect and
get_mode handlers.

Also a set of new port specific power domains are added so the above
encoder and connector specific check/get/put parts can refer to them.

One TODO item left is hot-plug detection on BYT. With the display power
well off HPD stops working and this patchset doesn't add any workaround
for that, as that wasn't deemed to be important. A solution to make it
work again would be to use connector polling for VGA and GPIO re-muxing
for DP,HDMI.

Another TODO is more power optimizations for DP 2 lane configurations
and configurations where only a single DP port is enabled. Since atm,
the PHY setup code assumes a two port/4 lanes config, we enable all
power domains that this requires. Atm, the only win is when all ports
are off, or in case of a single VGA connection, where we can power off
the DPIO TX lane power wells.

Tested on BYT DP/HDMI/VGA with xset dpms force off/on and suspend /
resume. Also did some basic testing on HSW,IVB with DP. I ransome of
the igt gem tests on BYT with all display power wells off, they
seemed to run ok.

Imre Deak (19):
  drm/i915: use drm_i915_private everywhere in the power domain api
  drm/i915: fold in __intel_power_well_get/put functions
  drm/i915: move modeset_update_power_wells earlier
  drm/i915: move power domain macros to intel_pm.c
  drm/i915: power domains: add power well ops
  drm/i915: remove power_well->always_on flag
  drm/i915: add port power domains
  drm/i915: get port power domain in connector detect
  drm/i915: check port power domain when reading the encoder hw state
  drm/i915: check pipe power domain when reading its hw state
  drm/i915: vlv: keep first level vblank IRQs masked
  drm/i915: sanitize PUNIT register macro definitions
  drm/i915: factor out reset_vblank_counter
  drm/i915: switch order of power domain init wrt. irq install
  drm/i915: use power domain api to check vga power state
  drm/i915: sanity check power well sw state against hw state
  drm/i915: vlv: factor out valleyview_display_irq_install
  drm/i915: move hsw power domain comment to its right place
  drm/i915: power domains: add vlv power wells

 drivers/gpu/drm/i915/i915_debugfs.c  |  22 ++
 drivers/gpu/drm/i915/i915_dma.c      |  16 +-
 drivers/gpu/drm/i915/i915_drv.c      |   4 +-
 drivers/gpu/drm/i915/i915_drv.h      |  65 ++++--
 drivers/gpu/drm/i915/i915_irq.c      | 126 +++++++---
 drivers/gpu/drm/i915/i915_reg.h      |  29 ++-
 drivers/gpu/drm/i915/intel_crt.c     |  42 +++-
 drivers/gpu/drm/i915/intel_ddi.c     |   2 +-
 drivers/gpu/drm/i915/intel_display.c | 255 +++++++++++++--------
 drivers/gpu/drm/i915/intel_dp.c      |  16 +-
 drivers/gpu/drm/i915/intel_drv.h     |  20 +-
 drivers/gpu/drm/i915/intel_dsi.c     |  13 +-
 drivers/gpu/drm/i915/intel_pm.c      | 433 +++++++++++++++++++++++++++++------
 drivers/gpu/drm/i915/intel_uncore.c  |   4 +-
 14 files changed, 797 insertions(+), 250 deletions(-)

-- 
1.8.4