[Intel-gfx] [PATCH 1/2] drm/i915: make sure south port interrupts are enabled properly

Paulo Zanoni przanoni at gmail.com
Fri Jan 10 22:10:38 CET 2014


2014/1/10 Jesse Barnes <jbarnes at virtuousgeek.org>:
> On Fri, 10 Jan 2014 13:02:20 -0800
> Jesse Barnes <jbarnes at virtuousgeek.org> wrote:
>
>> We were apparently relying on the defaults on BDW, which resulted in no
>> hotplug or AUX interrupts.
>>
>> References: https://bugs.freedesktop.org/show_bug.cgi?id=72834
>> References: https://bugs.freedesktop.org/show_bug.cgi?id=72833
>> Signed-off-by: Jesse Barnes <jbarnes at virtuousgeek.org>
>> ---
>>  drivers/gpu/drm/i915/i915_irq.c | 4 +++-
>>  1 file changed, 3 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
>> index 261254a..f88e265 100644
>> --- a/drivers/gpu/drm/i915/i915_irq.c
>> +++ b/drivers/gpu/drm/i915/i915_irq.c
>> @@ -2763,13 +2763,15 @@ static void ibx_irq_postinstall(struct drm_device *dev)
>>               mask = SDE_GMBUS | SDE_AUX_MASK | SDE_TRANSB_FIFO_UNDER |
>>                      SDE_TRANSA_FIFO_UNDER | SDE_POISON;
>>       } else {
>> -             mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT | SDE_ERROR_CPT;
>> +             mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT | SDE_ERROR_CPT |
>> +                     SDE_HOTPLUG_MASK_CPT;
>>
>>               I915_WRITE(SERR_INT, I915_READ(SERR_INT));
>>       }
>>
>>       I915_WRITE(SDEIIR, I915_READ(SDEIIR));
>>       I915_WRITE(SDEIMR, ~mask);
>> +     I915_WRITE(SDEIER, mask);
>>  }
>>
>>  static void gen5_gt_irq_postinstall(struct drm_device *dev)
>
> Note we still don't handle port A interrupts.  Not sure if that's
> important since we don't really use them yet, but if we want to add
> that we'd probably need to add some new code to the hpd functions to
> deal with walking both CPU and PCH masks.

All the previous gens also lack this and things kinda work so far...
The BIOS sets some state, and we lose it after suspend. Of course, I'm
not suggesting we should keep it like this :)


>
> --
> Jesse Barnes, Intel Open Source Technology Center
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-- 
Paulo Zanoni



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