[Intel-gfx] [PATCH 2/8] drm/i915: Add WaProgramL3SqcReg1Default:bdw

[Michel Thierry]

For performance, program the default initial value of L3SqcReg1 on BDW
to 0x784000:

L3SQ High Priority Credit Initialization = 2 (00001b).
L3SQ General Priority Credit Initialization = 30 (01111b).

Signed-off-by: Michel Thierry <michel.thierry at intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 4 ++++
 drivers/gpu/drm/i915/intel_pm.c | 3 +++
 2 files changed, 7 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index b8308cf..e813033 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4704,6 +4704,10 @@ enum punit_power_well {
 #define  HDC_FENCE_DESTINATION_TO_SLM_DISABLE	(1<<14)
 #define  HDC_FORCE_NON_COHERENT			(1<<4)
 
+/* WaProgramL3SqcReg1Default */
+#define GEN8_L3SQCREG1				0xb100
+#define  GEN8_L3SQCREG1_DEFAULT_VALUE	0x784000
+
 /* WaCatErrorRejectionIssue */
 #define GEN7_SQ_CHICKEN_MBCUNIT_CONFIG		0x9030
 #define  GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB	(1<<11)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 2c3087f..8b9abf4 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -5483,6 +5483,9 @@ static void gen8_init_clock_gating(struct drm_device *dev)
 	/* Wa4x4STCOptimizationDisable:bdw */
 	I915_WRITE(CACHE_MODE_1,
 		   _MASKED_BIT_ENABLE(GEN8_4x4_STC_OPTIMIZATION_DISABLE));
+
+	/* WaProgramL3SqcReg1Default:bdw */
+	I915_WRITE(GEN8_L3SQCREG1, GEN8_L3SQCREG1_DEFAULT_VALUE);
 }
 
 static void haswell_init_clock_gating(struct drm_device *dev)
-- 
1.9.0