[Intel-gfx] [PATCH 3/8] drm/i915: Add WaDisableFfDopClockGating:bdw

[Michel Thierry]

Disable FF DOP clock gating.

Signed-off-by: Michel Thierry <michel.thierry at intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 1 +
 drivers/gpu/drm/i915/intel_pm.c | 4 ++++
 2 files changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index e813033..44e7f34 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5600,6 +5600,7 @@ enum punit_power_well {
 #define   GEN6_RC7			4
 
 #define GEN7_MISCCPCTL			(0x9424)
+#define   GEN8_DOP_CLOCK_GATE_CFCLK_ENABLE	(1<<2)
 #define   GEN7_DOP_CLOCK_GATE_ENABLE	(1<<0)
 
 /* IVYBRIDGE DPF */
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 8b9abf4..6815680 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -5486,6 +5486,10 @@ static void gen8_init_clock_gating(struct drm_device *dev)
 
 	/* WaProgramL3SqcReg1Default:bdw */
 	I915_WRITE(GEN8_L3SQCREG1, GEN8_L3SQCREG1_DEFAULT_VALUE);
+
+	/* WaDisableFfDopClockGating:bdw */
+	I915_WRITE(GEN7_MISCCPCTL, I915_READ(GEN7_MISCCPCTL) &
+			~GEN8_DOP_CLOCK_GATE_CFCLK_ENABLE);
 }
 
 static void haswell_init_clock_gating(struct drm_device *dev)
-- 
1.9.0