[Intel-gfx] [PATCH v2 1/2] drm/i915: Set M2_N2 registers during mode set

Daniel Vetter daniel at ffwll.ch
Wed Jun 18 17:52:20 CEST 2014


On Wed, Jun 18, 2014 at 07:47:24PM +0530, Vandana Kannan wrote:
> For Gen < 8, set M2_N2 registers on every mode set. This is required to make
> sure M2_N2 registers are set during boot, resume from sleep for cross-
> checking the state. The register is set only if DRRS is supported.
> 
> v2: Patch rebased
> 
> Signed-off-by: Vandana Kannan <vandana.kannan at intel.com>
> Cc: Daniel Vetter <daniel.vetter at ffwll.ch>
> ---
>  drivers/gpu/drm/i915/i915_drv.h      |  3 +++
>  drivers/gpu/drm/i915/intel_display.c | 36 ++++++++++++++++++++++++++++++++----
>  drivers/gpu/drm/i915/intel_dp.c      | 14 --------------
>  drivers/gpu/drm/i915/intel_drv.h     |  1 +
>  4 files changed, 36 insertions(+), 18 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 0640071..6bf6e00 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1989,6 +1989,9 @@ struct drm_i915_cmd_table {
>  #define HAS_PSR(dev)		(IS_HASWELL(dev) || IS_BROADWELL(dev))
>  #define HAS_RUNTIME_PM(dev)	(IS_GEN6(dev) || IS_HASWELL(dev) || \
>  				 IS_BROADWELL(dev) || IS_VALLEYVIEW(dev))
> +#define HAS_DRRS(dev)		(to_i915(dev)->drrs.connector && \
> +				 to_i915(dev)->drrs.connector-> \
> +				 panel.downclock_mode)

Didn't spot this the first time around, but HAS_* macros should be chip
invariants, so no runtime-dependent pointer chasing and similar things
here. Which also means you can't use this in the pipe config checks.
Solution for that is to set pipe_config->has_drrs bool when you set the
2nd set of dp m/n values in the pipe_config in intel_dp_compute config.

My apologies that this takes so long and that the documentation for our
pipe-config infrastructure is so bad (= doesn't exist). I'm slowly working
towards the goal of document all the different subsystems in our driver.

Thanks, Daniel

>  
>  #define INTEL_PCH_DEVICE_ID_MASK		0xff00
>  #define INTEL_PCH_IBX_DEVICE_ID_TYPE		0x3b00
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 5e8e711..fca5e02 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -3987,8 +3987,12 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc)
>  	if (intel_crtc->config.has_pch_encoder)
>  		intel_prepare_shared_dpll(intel_crtc);
>  
> -	if (intel_crtc->config.has_dp_encoder)
> +	if (intel_crtc->config.has_dp_encoder) {
>  		intel_dp_set_m_n(intel_crtc);
> +		if (INTEL_INFO(dev)->gen < 8 && HAS_DRRS(dev))
> +			intel_dp_set_m2_n2(intel_crtc,
> +				&intel_crtc->config.dp_m2_n2);
> +	}
>  
>  	intel_set_pipe_timings(intel_crtc);
>  
> @@ -4097,8 +4101,12 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
>  	if (intel_crtc->active)
>  		return;
>  
> -	if (intel_crtc->config.has_dp_encoder)
> +	if (intel_crtc->config.has_dp_encoder) {
>  		intel_dp_set_m_n(intel_crtc);
> +		if (INTEL_INFO(dev)->gen < 8 && HAS_DRRS(dev))
> +			intel_dp_set_m2_n2(intel_crtc,
> +					&intel_crtc->config.dp_m2_n2);
> +	}
>  
>  	intel_set_pipe_timings(intel_crtc);
>  
> @@ -4614,8 +4622,12 @@ static void valleyview_crtc_enable(struct drm_crtc *crtc)
>  	/* Set up the display plane register */
>  	dspcntr = DISPPLANE_GAMMA_ENABLE;
>  
> -	if (intel_crtc->config.has_dp_encoder)
> +	if (intel_crtc->config.has_dp_encoder) {
>  		intel_dp_set_m_n(intel_crtc);
> +		if (INTEL_INFO(dev)->gen < 8 && HAS_DRRS(dev))
> +			intel_dp_set_m2_n2(intel_crtc,
> +					&intel_crtc->config.dp_m2_n2);
> +	}
>  
>  	intel_set_pipe_timings(intel_crtc);
>  
> @@ -4706,8 +4718,12 @@ static void i9xx_crtc_enable(struct drm_crtc *crtc)
>  	else
>  		dspcntr |= DISPPLANE_SEL_PIPE_B;
>  
> -	if (intel_crtc->config.has_dp_encoder)
> +	if (intel_crtc->config.has_dp_encoder) {
>  		intel_dp_set_m_n(intel_crtc);
> +		if (INTEL_INFO(dev)->gen < 8 && HAS_DRRS(dev))
> +			intel_dp_set_m2_n2(intel_crtc,
> +					&intel_crtc->config.dp_m2_n2);
> +	}
>  
>  	intel_set_pipe_timings(intel_crtc);
>  
> @@ -5494,6 +5510,18 @@ static void intel_dp_set_m_n(struct intel_crtc *crtc)
>  		intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
>  }
>  
> +void intel_dp_set_m2_n2(struct intel_crtc *crtc, struct intel_link_m_n *m_n)
> +{
> +	struct drm_device *dev = crtc->base.dev;
> +	struct drm_i915_private *dev_priv = dev->dev_private;
> +	enum transcoder transcoder = crtc->config.cpu_transcoder;
> +
> +	I915_WRITE(PIPE_DATA_M2(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
> +	I915_WRITE(PIPE_DATA_N2(transcoder), m_n->gmch_n);
> +	I915_WRITE(PIPE_LINK_M2(transcoder), m_n->link_m);
> +	I915_WRITE(PIPE_LINK_N2(transcoder), m_n->link_n);
> +}
> +
>  static void vlv_update_pll(struct intel_crtc *crtc)
>  {
>  	u32 dpll, dpll_md;
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 912e9c4..3394615 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -780,20 +780,6 @@ intel_dp_set_clock(struct intel_encoder *encoder,
>  	}
>  }
>  
> -static void
> -intel_dp_set_m2_n2(struct intel_crtc *crtc, struct intel_link_m_n *m_n)
> -{
> -	struct drm_device *dev = crtc->base.dev;
> -	struct drm_i915_private *dev_priv = dev->dev_private;
> -	enum transcoder transcoder = crtc->config.cpu_transcoder;
> -
> -	I915_WRITE(PIPE_DATA_M2(transcoder),
> -		TU_SIZE(m_n->tu) | m_n->gmch_m);
> -	I915_WRITE(PIPE_DATA_N2(transcoder), m_n->gmch_n);
> -	I915_WRITE(PIPE_LINK_M2(transcoder), m_n->link_m);
> -	I915_WRITE(PIPE_LINK_N2(transcoder), m_n->link_n);
> -}
> -
>  bool
>  intel_dp_compute_config(struct intel_encoder *encoder,
>  			struct intel_crtc_config *pipe_config)
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index ab5962b..cbdb71e 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -811,6 +811,7 @@ void intel_mode_from_pipe_config(struct drm_display_mode *mode,
>  				 struct intel_crtc_config *pipe_config);
>  int intel_format_to_fourcc(int format);
>  void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc);
> +void intel_dp_set_m2_n2(struct intel_crtc *crtc, struct intel_link_m_n *m_n);
>  
>  
>  /* intel_dp.c */
> -- 
> 1.9.3
> 

-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch



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