[Intel-gfx] [PATCH v3 1/2] drm/i915: Set M2_N2 registers during mode set

[Vandana Kannan]

For Gen < 8, set M2_N2 registers on every mode set. This is required to make
sure M2_N2 registers are set during boot, resume from sleep for cross-
checking the state. The register is set only if DRRS is supported.

v2: Patch rebased

v3: Daniel's review comments
	- Removed HAS_DRRS(dev) and added bool has_drrs to pipe_config to
	track drrs support

Signed-off-by: Vandana Kannan <vandana.kannan at intel.com>
Cc: Daniel Vetter <daniel.vetter at ffwll.ch>
---
 drivers/gpu/drm/i915/intel_display.c | 36 ++++++++++++++++++++++++++++++++----
 drivers/gpu/drm/i915/intel_dp.c      | 16 ++--------------
 drivers/gpu/drm/i915/intel_drv.h     |  2 ++
 3 files changed, 36 insertions(+), 18 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 5e8e711..2759be5 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3987,8 +3987,12 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc)
 	if (intel_crtc->config.has_pch_encoder)
 		intel_prepare_shared_dpll(intel_crtc);
 
-	if (intel_crtc->config.has_dp_encoder)
+	if (intel_crtc->config.has_dp_encoder) {
 		intel_dp_set_m_n(intel_crtc);
+		if (INTEL_INFO(dev)->gen < 8 && intel_crtc->config.has_drrs)
+			intel_dp_set_m2_n2(intel_crtc,
+				&intel_crtc->config.dp_m2_n2);
+	}
 
 	intel_set_pipe_timings(intel_crtc);
 
@@ -4097,8 +4101,12 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
 	if (intel_crtc->active)
 		return;
 
-	if (intel_crtc->config.has_dp_encoder)
+	if (intel_crtc->config.has_dp_encoder) {
 		intel_dp_set_m_n(intel_crtc);
+		if (INTEL_INFO(dev)->gen < 8 && intel_crtc->config.has_drrs)
+			intel_dp_set_m2_n2(intel_crtc,
+					&intel_crtc->config.dp_m2_n2);
+	}
 
 	intel_set_pipe_timings(intel_crtc);
 
@@ -4614,8 +4622,12 @@ static void valleyview_crtc_enable(struct drm_crtc *crtc)
 	/* Set up the display plane register */
 	dspcntr = DISPPLANE_GAMMA_ENABLE;
 
-	if (intel_crtc->config.has_dp_encoder)
+	if (intel_crtc->config.has_dp_encoder) {
 		intel_dp_set_m_n(intel_crtc);
+		if (INTEL_INFO(dev)->gen < 8 && intel_crtc->config.has_drrs)
+			intel_dp_set_m2_n2(intel_crtc,
+					&intel_crtc->config.dp_m2_n2);
+	}
 
 	intel_set_pipe_timings(intel_crtc);
 
@@ -4706,8 +4718,12 @@ static void i9xx_crtc_enable(struct drm_crtc *crtc)
 	else
 		dspcntr |= DISPPLANE_SEL_PIPE_B;
 
-	if (intel_crtc->config.has_dp_encoder)
+	if (intel_crtc->config.has_dp_encoder) {
 		intel_dp_set_m_n(intel_crtc);
+		if (INTEL_INFO(dev)->gen < 8 && intel_crtc->config.has_drrs)
+			intel_dp_set_m2_n2(intel_crtc,
+					&intel_crtc->config.dp_m2_n2);
+	}
 
 	intel_set_pipe_timings(intel_crtc);
 
@@ -5494,6 +5510,18 @@ static void intel_dp_set_m_n(struct intel_crtc *crtc)
 		intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
 }
 
+void intel_dp_set_m2_n2(struct intel_crtc *crtc, struct intel_link_m_n *m_n)
+{
+	struct drm_device *dev = crtc->base.dev;
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	enum transcoder transcoder = crtc->config.cpu_transcoder;
+
+	I915_WRITE(PIPE_DATA_M2(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
+	I915_WRITE(PIPE_DATA_N2(transcoder), m_n->gmch_n);
+	I915_WRITE(PIPE_LINK_M2(transcoder), m_n->link_m);
+	I915_WRITE(PIPE_LINK_N2(transcoder), m_n->link_n);
+}
+
 static void vlv_update_pll(struct intel_crtc *crtc)
 {
 	u32 dpll, dpll_md;
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 912e9c4..963ca49 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -780,20 +780,6 @@ intel_dp_set_clock(struct intel_encoder *encoder,
 	}
 }
 
-static void
-intel_dp_set_m2_n2(struct intel_crtc *crtc, struct intel_link_m_n *m_n)
-{
-	struct drm_device *dev = crtc->base.dev;
-	struct drm_i915_private *dev_priv = dev->dev_private;
-	enum transcoder transcoder = crtc->config.cpu_transcoder;
-
-	I915_WRITE(PIPE_DATA_M2(transcoder),
-		TU_SIZE(m_n->tu) | m_n->gmch_m);
-	I915_WRITE(PIPE_DATA_N2(transcoder), m_n->gmch_n);
-	I915_WRITE(PIPE_LINK_M2(transcoder), m_n->link_m);
-	I915_WRITE(PIPE_LINK_N2(transcoder), m_n->link_n);
-}
-
 bool
 intel_dp_compute_config(struct intel_encoder *encoder,
 			struct intel_crtc_config *pipe_config)
@@ -819,6 +805,7 @@ intel_dp_compute_config(struct intel_encoder *encoder,
 		pipe_config->has_pch_encoder = true;
 
 	pipe_config->has_dp_encoder = true;
+	pipe_config->has_drrs = false;
 	pipe_config->has_audio = intel_dp->has_audio;
 
 	if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
@@ -922,6 +909,7 @@ found:
 
 	if (intel_connector->panel.downclock_mode != NULL &&
 		intel_dp->drrs_state.type == SEAMLESS_DRRS_SUPPORT) {
+			pipe_config->has_drrs = true;
 			intel_link_compute_m_n(bpp, lane_count,
 				intel_connector->panel.downclock_mode->clock,
 				pipe_config->port_clock,
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index ab5962b..eed0b74 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -315,6 +315,7 @@ struct intel_crtc_config {
 
 	/* m2_n2 for eDP downclock */
 	struct intel_link_m_n dp_m2_n2;
+	bool has_drrs;
 
 	/*
 	 * Frequence the dpll for the port should run at. Differs from the
@@ -811,6 +812,7 @@ void intel_mode_from_pipe_config(struct drm_display_mode *mode,
 				 struct intel_crtc_config *pipe_config);
 int intel_format_to_fourcc(int format);
 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc);
+void intel_dp_set_m2_n2(struct intel_crtc *crtc, struct intel_link_m_n *m_n);
 
 
 /* intel_dp.c */
-- 
1.9.3