[Intel-gfx] [PATCH 39/49] drm/i915/bdw: Swap the PPGTT PDPs, LRC style

[Damien Lespiau]

On Thu, Mar 27, 2014 at 06:00:08PM +0000, oscar.mateo at intel.com wrote:
> +	reg_state[CTX_PDP3_UDW+1] = ppgtt->pd_dma_addr[3] >> 32;
> +	reg_state[CTX_PDP3_LDW+1] = ppgtt->pd_dma_addr[3];
> +	reg_state[CTX_PDP2_UDW+1] = ppgtt->pd_dma_addr[2] >> 32;
> +	reg_state[CTX_PDP2_LDW+1] = ppgtt->pd_dma_addr[2];
> +	reg_state[CTX_PDP1_UDW+1] = ppgtt->pd_dma_addr[1] >> 32;
> +	reg_state[CTX_PDP1_LDW+1] = ppgtt->pd_dma_addr[1];
> +	reg_state[CTX_PDP0_UDW+1] = ppgtt->pd_dma_addr[0] >> 32;
> +	reg_state[CTX_PDP0_LDW+1] = ppgtt->pd_dma_addr[0];

Compiling a 32bits kernel whithout HIGHMEM64G gives:

drivers/gpu/drm/i915/i915_lrc.c: In function ‘gen8_write_pdp_ctx’:
drivers/gpu/drm/i915/i915_lrc.c:286:2: warning: right shift count >=
width of type [enabled by default]
  reg_state[CTX_PDP3_UDW+1] = ppgtt->pd_dma_addr[3] >> 32;

Turns out dma_addr_t can be 32bits if configured without 64bits support
on 32bits kernels:

#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
typedef u64 dma_addr_t;
#else           
typedef u32 dma_addr_t;
#endif /* dma_addr_t *

and

config ARCH_DMA_ADDR_T_64BIT
        def_bool y
        depends on X86_64 || HIGHMEM64G

-- 
Damien