[Intel-gfx] [PATCH 0/4] SKL eDP clocks

[Damien Lespiau]

On Mon, Nov 17, 2014 at 03:04:19PM -0200, Paulo Zanoni wrote:
> 2014-11-14 15:24 GMT-02:00 Damien Lespiau <damien.lespiau at intel.com>:
> > The previous clock series didn't include the eDP side of it. This should
> > address most of it, for now.
> >
> > Note that I have some issues with HBR2 and link training here and I'm trying to
> > find more information about this. So depending on the configuration (number of
> > lanes wired, panel bw) this series may not be enough to light up an eDP panel.
> 
> I couldn't spot anything obvious here...
> 
> For all patches: Reviewed-by: Paulo Zanoni <paulo.r.zanoni at intel.com>

Thanks!

> My bikeshedding would be to replace the magic "(id * 6)" - from
> patches 2 and 4 - and "0x3f" - from patch 4 - with some nice macro
> definitions.

Yes, that's also the case for the rest of the SKL DPLL code, the plan is
to fix that on top.

-- 
Damien