[Intel-gfx] [PATCH 0/4] SKL eDP clocks

[Paulo Zanoni]

2014-11-14 15:24 GMT-02:00 Damien Lespiau <damien.lespiau at intel.com>:
> The previous clock series didn't include the eDP side of it. This should
> address most of it, for now.
>
> Note that I have some issues with HBR2 and link training here and I'm trying to
> find more information about this. So depending on the configuration (number of
> lanes wired, panel bw) this series may not be enough to light up an eDP panel.

I couldn't spot anything obvious here...

For all patches: Reviewed-by: Paulo Zanoni <paulo.r.zanoni at intel.com>

My bikeshedding would be to replace the magic "(id * 6)" - from
patches 2 and 4 - and "0x3f" - from patch 4 - with some nice macro
definitions.

>
> --
> Damien
>
> Damien Lespiau (4):
>   drm/i915/skl: Remove spurious warn in get_ddi_pll()
>   drm/i915/skl: Set the eDP link rate on DPLL0
>   drm/i915/skl: Use the pipe config DPLL tracking to query the link
>     clock
>   drm/i915/skl: Read out crtl1 for eDP/DPLL0
>
>  drivers/gpu/drm/i915/intel_ddi.c     | 34 +++++++++++++++++++++++++++++-----
>  drivers/gpu/drm/i915/intel_display.c |  2 --
>  drivers/gpu/drm/i915/intel_dp.c      | 31 ++++++++++++++++++++++++++++++-
>  3 files changed, 59 insertions(+), 8 deletions(-)
>
> --
> 1.8.3.1
>
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-- 
Paulo Zanoni