[Intel-gfx] [PATCH 65/89] drm/i915/skl: Always use DPLL0 for eDP

[M, Satheeshakrishna]

On 9/23/2014 8:37 PM, Paulo Zanoni wrote:
> 2014-09-04 8:27 GMT-03:00 Damien Lespiau<damien.lespiau at intel.com>:
>> From: Satheeshakrishna M<satheeshakrishna.m at intel.com>
>>
>> DPLL0 is not part of the shared PLL infrastructure. We'll use on for
>> eDP and rely on what the BIOS does for now.
>>
>> Signed-off-by: Satheeshakrishna M<satheeshakrishna.m at intel.com>
>> Signed-off-by: Damien Lespiau<damien.lespiau at intel.com>
>> ---
>>   drivers/gpu/drm/i915/intel_dp.c | 5 ++++-
>>   1 file changed, 4 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
>> index 5755f59..93bd9bf 100644
>> --- a/drivers/gpu/drm/i915/intel_dp.c
>> +++ b/drivers/gpu/drm/i915/intel_dp.c
>> @@ -1005,7 +1005,10 @@ found:
>>                                  &pipe_config->dp_m2_n2);
>>          }
>>
>> -       if (IS_HASWELL(dev) || IS_BROADWELL(dev))
>> +       if (IS_SKYLAKE(dev)) {
>> +               if (is_edp(intel_dp))
>> +                       pipe_config->ddi_pll_sel = SKL_DPLL0;
> So we just don't assign anything else for the other ports? Why exactly?
Other ports follow the shared dpll logic and assignment happens in intel_ddi
>
>> +       } else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
>>                  hsw_dp_set_ddi_pll_sel(pipe_config, intel_dp->link_bw);
>>          else
>>                  intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw);
>> --
>> 1.8.3.1
>>
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>