[Intel-gfx] [PATCH 1/2] drm/i915/chv: Add few more CHV workarounds

[Siluvery, Arun]

On 28/10/2014 12:23, Ville Syrjälä wrote:
> On Tue, Oct 28, 2014 at 11:57:50AM +0000, Arun Siluvery wrote:
>> WaDisableInstructionShootdown:chv
>> WaForceEnableNonCoherent:chv
>> WaHdcDisableFetchWhenMasked:chv
>> WaDisableFenceDestinationToSLM:chv (pre-production)
>>
>> s/WaDisableDopClockGating/WaDisableRowChickenDopClockGating, because another
>> CHV WA is defined with the same name in intel_pm.c for a different reg.
>>
>> For: VIZ-4090
>> Signed-off-by: Arun Siluvery <arun.siluvery at linux.intel.com>
>> ---
>>   drivers/gpu/drm/i915/i915_reg.h         |  2 ++
>>   drivers/gpu/drm/i915/intel_ringbuffer.c | 20 ++++++++++++++++++--
>>   2 files changed, 20 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>> index 77fce96..840e5d9 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -5024,6 +5024,7 @@ enum punit_power_well {
>>   /* GEN8 chicken */
>>   #define HDC_CHICKEN0				0x7300
>>   #define  HDC_FORCE_NON_COHERENT			(1<<4)
>> +#define  HDC_DONOT_FETCH_MEM_WHEN_MASKED	(1<<11)
>>   #define  HDC_FENCE_DEST_SLM_DISABLE		(1<<14)
>>
>>   /* WaCatErrorRejectionIssue */
>> @@ -5941,6 +5942,7 @@ enum punit_power_well {
>>   #define   GEN9_DG_MIRROR_FIX_ENABLE	(1<<5)
>>
>>   #define GEN8_ROW_CHICKEN		0xe4f0
>> +#define   INSTRUCTION_SHOOTDOWN_DISABLE (1<<9)
>>   #define   PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE	(1<<8)
>>   #define   STALL_DOP_GATING_DISABLE		(1<<5)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
>> index a8f72e8..2c07a02 100644
>> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
>> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
>> @@ -788,14 +788,30 @@ static int chv_init_workarounds(struct intel_engine_cs *ring)
>>   	struct drm_i915_private *dev_priv = dev->dev_private;
>>
>>   	/* WaDisablePartialInstShootdown:chv */
>> +	/* WaDisableInstructionShootdown:chv */
>>   	WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
>> -		  PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);
>> +			  PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE |
>> +			  (dev->pdev->revision < 0x06 ?
>> +			   INSTRUCTION_SHOOTDOWN_DISABLE : 0));
>
> I think we should just drop the current early pre-prod workarounds, and
> not add more of them.
>
ok I will drop this.
Is there any guideline on particular revision for bdw, chv below which 
we should drop that workaround?

>>
>>   	/* WaDisableThreadStallDopClockGating:chv */
>>   	WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
>>   		  STALL_DOP_GATING_DISABLE);
>>
>> -	/* WaDisableDopClockGating:chv (pre-production hw) */
>> +	/* Use Force Non-Coherent whenever executing a 3D context. This is a
>> +	 * workaround for a possible hang in the unlikely event a TLB
>> +	 * invalidation occurs during a PSD flush.
>> +	 */
>
> We haven't generally documented the w/as in any great detail. Does it
> help someone if we start doing that?

This was already documented for bdw hence I included it for chv also.

regards
Arun

>
>> +	/* WaForceEnableNonCoherent:chv */
>> +	/* WaHdcDisableFetchWhenMasked:chv */
>> +	/* WaDisableFenceDestinationToSLM:chv (pre-production) */
>> +	WA_SET_BIT_MASKED(HDC_CHICKEN0,
>> +			  HDC_FORCE_NON_COHERENT |
>> +			  HDC_DONOT_FETCH_MEM_WHEN_MASKED |
>> +			  (dev->pdev->revision < 0x06 ?
>> +			   HDC_FENCE_DEST_SLM_DISABLE : 0));
>> +
>> +	/* WaDisableRowChickenDopClockGating:chv (pre-production hw) */
>>   	WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,
>>   		  DOP_CLOCK_GATING_DISABLE);
>>
>> --
>> 2.1.2
>>
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>