[Intel-gfx] [PATCH 2/2] drm/i915: Minimize the huge amount of unecessary fbc sw cache clean.
Rodrigo Vivi
rodrigo.vivi at gmail.com
Wed Sep 17 22:36:03 CEST 2014
Please just ignore my latest comment here...
I confirm this works propperly with the PSR with my latest fixes...
On Fri, Sep 5, 2014 at 3:14 PM, Rodrigo Vivi <rodrigo.vivi at gmail.com> wrote:
> Hey Daniel,
>
> funny story: Remember that with idle_frames=1 on BDW it was working but it
> was faililng on HSW?
> So, with these 2 patches applied now BDW PSR fails like HSW!!!
>
> Ville, any thoughts on this?
>
>
> On Fri, Sep 5, 2014 at 1:57 PM, Rodrigo Vivi <rodrigo.vivi at intel.com>
> wrote:
>
>> The sw cache clean on gen8 is a tempoorary workaround because we cannot
>> set cache clean on blt ring with risk of hungs. So we are doing the cache
>> clean on sw.
>> However we are doing much more than needed. Not only when using blt ring.
>> So, with this extra w/a we minimize the ammount of cache cleans and call
>> it only
>> on same cases that it was being called on gen7.
>>
>> fbc.need_sw_cache_clean works in the opposite information direction
>> of ring->fbc_dirty telling software on frontbuffer tracking to perform
>> the cache clean on sw side.
>>
>> Cc: Paulo Zanoni <paulo.r.zanoni at intel.com>
>> Signed-off-by: Rodrigo Vivi <rodrigo.vivi at intel.com>
>> ---
>> drivers/gpu/drm/i915/i915_drv.h | 8 ++++++++
>> drivers/gpu/drm/i915/intel_display.c | 4 +++-
>> drivers/gpu/drm/i915/intel_ringbuffer.c | 9 +++++++--
>> 3 files changed, 18 insertions(+), 3 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_drv.h
>> b/drivers/gpu/drm/i915/i915_drv.h
>> index 5706b8a..5acda40 100644
>> --- a/drivers/gpu/drm/i915/i915_drv.h
>> +++ b/drivers/gpu/drm/i915/i915_drv.h
>> @@ -657,6 +657,14 @@ struct i915_fbc {
>>
>> bool false_color;
>>
>> + /* On gen8 some rings cannont perform fbc clean operation so for
>> now
>> + * we are doing this on SW with mmio.
>> + * This variable works in the opposite information direction
>> + * of ring->fbc_dirty telling software on frontbuffer tracking
>> + * to perform the cache clean on sw side.
>> + */
>> + bool need_sw_cache_clean;
>> +
>> struct intel_fbc_work {
>> struct delayed_work work;
>> struct drm_crtc *crtc;
>> diff --git a/drivers/gpu/drm/i915/intel_display.c
>> b/drivers/gpu/drm/i915/intel_display.c
>> index 965eb3c..731d925 100644
>> --- a/drivers/gpu/drm/i915/intel_display.c
>> +++ b/drivers/gpu/drm/i915/intel_display.c
>> @@ -9137,8 +9137,10 @@ void intel_frontbuffer_flush(struct drm_device
>> *dev,
>> * needs to be reworked into a proper frontbuffer tracking scheme
>> like
>> * psr employs.
>> */
>> - if (IS_BROADWELL(dev))
>> + if (IS_BROADWELL(dev) && dev_priv->fbc.need_sw_cache_clean) {
>> + dev_priv->fbc.need_sw_cache_clean = false;
>> gen8_fbc_sw_flush(dev, FBC_REND_CACHE_CLEAN);
>> + }
>> }
>>
>> /**
>> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c
>> b/drivers/gpu/drm/i915/intel_ringbuffer.c
>> index 85fc2b1..02b43cd 100644
>> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
>> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
>> @@ -2227,6 +2227,7 @@ static int gen6_ring_flush(struct intel_engine_cs
>> *ring,
>> u32 invalidate, u32 flush)
>> {
>> struct drm_device *dev = ring->dev;
>> + struct drm_i915_private *dev_priv = dev->dev_private;
>> uint32_t cmd;
>> int ret;
>>
>> @@ -2257,8 +2258,12 @@ static int gen6_ring_flush(struct intel_engine_cs
>> *ring,
>> }
>> intel_ring_advance(ring);
>>
>> - if (IS_GEN7(dev) && !invalidate && flush)
>> - return gen7_ring_fbc_flush(ring, FBC_REND_CACHE_CLEAN);
>> + if (!invalidate && flush) {
>> + if (IS_GEN7(dev))
>> + return gen7_ring_fbc_flush(ring,
>> FBC_REND_CACHE_CLEAN);
>> + else if (IS_GEN8(dev))
>> + dev_priv->fbc.need_sw_cache_clean = true;
>> + }
>>
>> return 0;
>> }
>> --
>> 1.9.3
>>
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx at lists.freedesktop.org
>> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>>
>
>
>
> --
> Rodrigo Vivi
> Blog: http://blog.vivi.eng.br
>
>
--
Rodrigo Vivi
Blog: http://blog.vivi.eng.br
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