[Intel-gfx] [PATCH] drm/i915/chv: Implement Wa4x4STCOptimizationDisable:chv

[Ville Syrjälä]

On Wed, Sep 17, 2014 at 05:03:02AM -0700, Rodrigo Vivi wrote:
> Cc: Ville Syrjälä <ville.syrjala at linux.intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi at intel.com>
> ---
>  drivers/gpu/drm/i915/intel_ringbuffer.c | 4 ++++
>  1 file changed, 4 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index 4e8b2ea..50d9169 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -784,6 +784,10 @@ static int chv_init_workarounds(struct intel_engine_cs *ring)
>  	intel_ring_emit_wa(ring, GEN8_ROW_CHICKEN,
>  			   _MASKED_BIT_ENABLE(STALL_DOP_GATING_DISABLE));
>  
> +	/* Wa4x4STCOptimizationDisable:chv */
> +	intel_ring_emit_wa(ring, CACHE_MODE_1,
> +			   _MASKED_BIT_ENABLE(GEN8_4x4_STC_OPTIMIZATION_DISABLE));
> +

Let's try to keep these in some order shall we. So please put this as
the last w/a.

Also you need to reserve more ring space, and because the ring tail must
be QW aligned you need to toss in a MI_NOOP when the number of wa emits
is odd. Maybe we should try to avoid future churn here and do something
like:

int num_wa = 5;

intel_ring_begin(ALIGN(num_wa * 3, 2));

intel_ring_emit_wa(...);
...

if ((num_wa * 3) & 1)
	ring_emit(MI_NOOP);

intel_ring_advance();


>  	/* WaDisableDopClockGating:chv (pre-production hw) */
>  	intel_ring_emit_wa(ring, GEN7_ROW_CHICKEN2,
>  			   _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
> -- 
> 1.9.3

-- 
Ville Syrjälä
Intel OTC