[Intel-gfx] [PATCH 03/70] drm/i915: Ensure cache flushes prior to doing CS flips

[Chris Wilson]

On Wed, Apr 08, 2015 at 01:23:50PM +0200, Daniel Vetter wrote:
> On Tue, Apr 07, 2015 at 04:20:27PM +0100, Chris Wilson wrote:
> > Synchronising to an object active on the same ring is a no-op, for the
> > benefit of execbuffer scheduler. However, for CS flips this means that
> > we can forgo checking whether the last write request of the object is
> > actually queued and more importantly whether the cache flush for the
> > write was emitted.
> > 
> > Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
> 
> Does this go boom in reality, i.e. bugzilla/igt? If so I guess this should
> be for 4.1+cc:stable? Otherwise I think I'll punt since olr is on its
> demise anyway.

Who can say for sure? Maybe
https://bugs.freedesktop.org/show_bug.cgi?id=80948 it is cache dirt(?)
without a known cause.
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre