[Intel-gfx] [PATCH] drm/i915/vlv: Modifying RC6 Promotion timer for Media workloads.

[Namrta Salonie]

In normal cases, RC6 promotion timer is 1700us. This will result in more
time spent in C1 state. For more residency in C6 in case of media workloads,
this is changed to 250us. Not doing this for 3D workloads as too many C6-C0
transition delays can result in performance impact. Tracking the media
workloads based on command submission to MFX engine.

Signed-off-by: Namrta Salonie <namrta.salonie at intel.com>
Signed-off-by: Satyanantha, Rama Gopal M <rama.gopal.m.satyanantha at intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h            |    3 +++
 drivers/gpu/drm/i915/i915_gem_execbuffer.c |   14 +++++++++++++
 drivers/gpu/drm/i915/i915_reg.h            |    2 ++
 drivers/gpu/drm/i915/intel_drv.h           |    2 ++
 drivers/gpu/drm/i915/intel_pm.c            |   30 +++++++++++++++++++++++++++-
 5 files changed, 50 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index bc865e23..74c9f86 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1147,6 +1147,9 @@ struct intel_gen6_power_mgmt {
 	 * talking to hw - so only take it when talking to hw!
 	 */
 	struct mutex hw_lock;
+
+	/* Delayed work to adjust RC6 promotion timer */
+	struct delayed_work vlv_media_timeout_work;
 };
 
 /* defined intel_pm.c */
diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index a4c243c..af7fbf8 100644
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -1254,6 +1254,20 @@ i915_gem_ringbuffer_submission(struct i915_execbuffer_params *params,
 			return ret;
 	}
 
+	/* For VLV, modify RC6 promotion timer upon hitting Media workload only
+	   This will help in better power savings with media scenarios.
+	 */
+	if (((args->flags & I915_EXEC_RING_MASK) == I915_EXEC_BSD) &&
+			!IS_CHERRYVIEW(dev) && IS_VALLEYVIEW(dev) &&
+			dev_priv->rps.enabled) {
+		vlv_modify_rc6_promotion_timer(dev_priv, true);
+
+		/*Start a timer for 1 sec to reset this value to original*/
+		mod_delayed_work(dev_priv->wq,
+				&dev_priv->rps.vlv_media_timeout_work,
+				msecs_to_jiffies(1000));
+	}
+
 	exec_len   = args->batch_len;
 	exec_start = params->batch_obj_vm_offset +
 		     params->args_batch_start_offset;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 4872245..3f66f5d 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6905,6 +6905,8 @@ enum skl_disp_power_wells {
 #define GEN6_RCUBMABDTMR			_MMIO(0xA0B0)
 #define GEN6_RC1e_THRESHOLD			_MMIO(0xA0B4)
 #define GEN6_RC6_THRESHOLD			_MMIO(0xA0B8)
+#define GEN6_RC6_RENDER_PROMOTION_TIMER_TO      0x0557
+#define GEN6_RC6_MEDIA_PROMOTION_TIMER_TO       0x00C3
 #define GEN6_RC6p_THRESHOLD			_MMIO(0xA0BC)
 #define VLV_RCEDATA				_MMIO(0xA0BC)
 #define GEN6_RC6pp_THRESHOLD			_MMIO(0xA0C0)
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 8fae824..e563d65 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1283,6 +1283,8 @@ void intel_dsi_init(struct drm_device *dev);
 /* intel_dvo.c */
 void intel_dvo_init(struct drm_device *dev);
 
+extern void vlv_modify_rc6_promotion_timer(struct drm_i915_private *dev_priv,
+					   bool media_active);
 
 /* legacy fbdev emulation in intel_fbdev.c */
 #ifdef CONFIG_DRM_FBDEV_EMULATION
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 1c1ea63..149b944 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4492,6 +4492,26 @@ static void valleyview_disable_rps(struct drm_device *dev)
 	intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
 }
 
+void vlv_modify_rc6_promotion_timer(struct drm_i915_private *dev_priv,
+		bool media_active)
+{
+	/* Update RC6 promotion timers */
+	if (media_active)
+		I915_WRITE(GEN6_RC6_THRESHOLD,
+				GEN6_RC6_MEDIA_PROMOTION_TIMER_TO);
+	else
+		I915_WRITE(GEN6_RC6_THRESHOLD,
+				GEN6_RC6_RENDER_PROMOTION_TIMER_TO);
+}
+
+static void vlv_media_timeout_work_func(struct work_struct *work)
+{
+	struct drm_i915_private *dev_priv = container_of(work, struct drm_i915_private,
+			rps.vlv_media_timeout_work.work);
+
+	vlv_modify_rc6_promotion_timer(dev_priv, false);
+}
+
 static void intel_print_rc6_info(struct drm_device *dev, u32 mode)
 {
 	if (IS_VALLEYVIEW(dev)) {
@@ -6050,7 +6070,9 @@ static void gen6_suspend_rps(struct drm_device *dev)
 	struct drm_i915_private *dev_priv = dev->dev_private;
 
 	flush_delayed_work(&dev_priv->rps.delayed_resume_work);
-
+	/*Cancel any pending work-item*/
+	cancel_delayed_work_sync(&dev_priv->rps.vlv_media_timeout_work);
+	
 	gen6_disable_rps_interrupts(dev);
 }
 
@@ -7258,6 +7280,12 @@ void intel_pm_setup(struct drm_device *dev)
 
 	INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work,
 			  intel_gen6_powersave_work);
+	/* Initialize a work item to modify RC6 promotion timer
+	 * based on MFX engine activity
+	 */
+	INIT_DELAYED_WORK(&dev_priv->rps.vlv_media_timeout_work,
+			vlv_media_timeout_work_func);
+
 	INIT_LIST_HEAD(&dev_priv->rps.clients);
 	INIT_LIST_HEAD(&dev_priv->rps.semaphores.link);
 	INIT_LIST_HEAD(&dev_priv->rps.mmioflips.link);
-- 
1.7.9.5