[Intel-gfx] [PATCH 5/7] drm/i915/skl: Updated the gen9_enable_rps function

[Damien Lespiau]

On Fri, Feb 06, 2015 at 08:26:36PM +0530, akash.goel at intel.com wrote:
> From: Akash Goel <akash.goel at intel.com>
> 
> On SKL, GT frequency is programmed in units of 16.66 MHZ units compared
> to 50 MHZ for older platforms. Also the time value specified for Up/Down EI &
> Up/Down thresholds are expressed in units of 1.33 us, compared to 1.28
> us for older platforms. So updated the gen9_enable_rps function as per that.
> 
> Signed-off-by: Akash Goel <akash.goel at intel.com>

The function was following exactly what is in the PM programming guide,
so it should be correct, not sure we want to change that. Your version
looks more readable though. 

I think I'd rather keep the close to the PM guide, but others may
disagree.

-- 
Damien

> ---
>  drivers/gpu/drm/i915/intel_pm.c | 41 ++++++++++++++++++++++++++++++++---------
>  1 file changed, 32 insertions(+), 9 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index db24b48..865df1f 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4037,27 +4037,50 @@ static void gen6_init_rps_frequencies(struct drm_device *dev)
>  static void gen9_enable_rps(struct drm_device *dev)
>  {
>  	struct drm_i915_private *dev_priv = dev->dev_private;
> +	u32 threshold_up_pct, threshold_down_pct;
> +	u32 ei_up, ei_down;
>  
>  	intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
>  
>  	gen6_init_rps_frequencies(dev);
>  
> -	I915_WRITE(GEN6_RPNSWREQ, 0xc800000);
> -	I915_WRITE(GEN6_RC_VIDEO_FREQ, 0xc800000);
> +	/* Program defaults and thresholds for RPS*/
> +	I915_WRITE(GEN6_RPNSWREQ,
> +		GEN9_FREQUENCY(dev_priv->rps.rp1_freq * GEN9_FREQ_SCALER));
> +	I915_WRITE(GEN6_RC_VIDEO_FREQ,
> +		GEN9_FREQUENCY(dev_priv->rps.rp1_freq * GEN9_FREQ_SCALER));
> +
> +	ei_up = 84480; /* 84.48ms */
> +	ei_down = 448000;
> +	threshold_up_pct = 90; /* x% */
> +	threshold_down_pct = 70;
> +
> +	I915_WRITE(GEN6_RP_UP_EI,
> +		GT_FREQ_FROM_PERIOD(ei_up, dev));
> +	I915_WRITE(GEN6_RP_UP_THRESHOLD,
> +		GT_FREQ_FROM_PERIOD((ei_up * threshold_up_pct / 100), dev));
> +
> +	I915_WRITE(GEN6_RP_DOWN_EI,
> +		GT_FREQ_FROM_PERIOD(ei_down, dev));
> +	I915_WRITE(GEN6_RP_DOWN_THRESHOLD,
> +		GT_FREQ_FROM_PERIOD((ei_down * threshold_down_pct / 100), dev));
> +
> +	/* 1 second timeout*/
> +	I915_WRITE(GEN6_RP_DOWN_TIMEOUT, GT_FREQ_FROM_PERIOD(1000000, dev));
> +
> +	I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
> +		(dev_priv->rps.max_freq_softlimit * GEN9_FREQ_SCALER) << 23 |
> +		(dev_priv->rps.min_freq_softlimit * GEN9_FREQ_SCALER) << 14);
>  
> -	I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 0xf4240);
> -	I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, 0x12060000);
> -	I915_WRITE(GEN6_RP_UP_THRESHOLD, 0xe808);
> -	I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 0x3bd08);
> -	I915_WRITE(GEN6_RP_UP_EI, 0x101d0);
> -	I915_WRITE(GEN6_RP_DOWN_EI, 0x55730);
>  	I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 0xa);
> -	I915_WRITE(GEN6_PMINTRMSK, 0x6);
>  	I915_WRITE(GEN6_RP_CONTROL, GEN6_RP_MEDIA_TURBO |
>  		   GEN6_RP_MEDIA_HW_MODE | GEN6_RP_MEDIA_IS_GFX |
>  		   GEN6_RP_ENABLE | GEN6_RP_UP_BUSY_AVG |
>  		   GEN6_RP_DOWN_IDLE_AVG);
>  
> +	dev_priv->rps.power = HIGH_POWER; /* force a reset */
> +	gen6_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);
> +
>  	gen6_enable_rps_interrupts(dev);
>  
>  	intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
> -- 
> 1.9.2
>