[Intel-gfx] [PATCH v2 1/3] drm/i915/chv: Populate total EU count on Cherryview

[Ville Syrjälä]

On Fri, Jan 16, 2015 at 08:42:16PM +0530, deepak.s at linux.intel.com wrote:
> From: Deepak S <deepak.s at linux.intel.com>
> 
> Starting with Cherryview, devices may have a varying number of EU for
> a given ID due to creative fusing. Punit support different frequency for
> different fuse data. We use this patch to help get total eu enabled and
> read the right offset to get RP0
> 
> Based upon a patch from Jeff, but reworked to only store eu_total and
> avoid sending info to userspace
> 
> v2: Format register definitions (Jani)
> 
> Signed-off-by: Deepak S <deepak.s at linux.intel.com>
> Signed-off-by: Jeff McGee <jeff.mcgee at intel.com>

Reviewed-by: Ville Syrjälä <ville.syrjala at linux.intel.com>

> ---
>  drivers/gpu/drm/i915/i915_dma.c | 11 +++++++++++
>  drivers/gpu/drm/i915/i915_drv.h |  1 +
>  drivers/gpu/drm/i915/i915_reg.h | 11 +++++++++++
>  3 files changed, 23 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
> index 2447de3..b868e9d 100644
> --- a/drivers/gpu/drm/i915/i915_dma.c
> +++ b/drivers/gpu/drm/i915/i915_dma.c
> @@ -601,6 +601,17 @@ static void intel_device_info_runtime_init(struct drm_device *dev)
>  			info->num_pipes = 0;
>  		}
>  	}
> +
> +	if (IS_CHERRYVIEW(dev)) {
> +		u32 fuse, mask_eu;
> +
> +		fuse = I915_READ(CHV_FUSE_GT);
> +		mask_eu = fuse & (CHV_FGT_EU_DIS_SS0_R0_MASK |
> +				  CHV_FGT_EU_DIS_SS0_R1_MASK |
> +				  CHV_FGT_EU_DIS_SS1_R0_MASK |
> +				  CHV_FGT_EU_DIS_SS1_R1_MASK);
> +		info->eu_total = 16 - hweight32(mask_eu);
> +	}
>  }
>  
>  /**
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 66f0c60..ab1fa9e 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -653,6 +653,7 @@ struct intel_device_info {
>  	int trans_offsets[I915_MAX_TRANSCODERS];
>  	int palette_offsets[I915_MAX_PIPES];
>  	int cursor_offsets[I915_MAX_PIPES];
> +	unsigned int eu_total;
>  };
>  
>  #undef DEFINE_FLAG
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index a39bb03..d9692f9 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1471,6 +1471,17 @@ enum punit_power_well {
>  #define   GEN8_RC_SEMA_IDLE_MSG_DISABLE	(1 << 12)
>  #define   GEN8_FF_DOP_CLOCK_GATE_DISABLE	(1<<10)
>  
> +/* Fuse readout registers for GT */
> +#define CHV_FUSE_GT			(VLV_DISPLAY_BASE + 0x2168)
> +#define   CHV_FGT_EU_DIS_SS0_R0_SHIFT	16
> +#define   CHV_FGT_EU_DIS_SS0_R0_MASK	(0xf << CHV_FGT_EU_DIS_SS0_R0_SHIFT)
> +#define   CHV_FGT_EU_DIS_SS0_R1_SHIFT	20
> +#define   CHV_FGT_EU_DIS_SS0_R1_MASK	(0xf << CHV_FGT_EU_DIS_SS0_R1_SHIFT)
> +#define   CHV_FGT_EU_DIS_SS1_R0_SHIFT	24
> +#define   CHV_FGT_EU_DIS_SS1_R0_MASK	(0xf << CHV_FGT_EU_DIS_SS1_R0_SHIFT)
> +#define   CHV_FGT_EU_DIS_SS1_R1_SHIFT	28
> +#define   CHV_FGT_EU_DIS_SS1_R1_MASK	(0xf << CHV_FGT_EU_DIS_SS1_R1_SHIFT)
> +
>  #define GEN6_BSD_SLEEP_PSMI_CONTROL	0x12050
>  #define   GEN6_BSD_SLEEP_MSG_DISABLE	(1 << 0)
>  #define   GEN6_BSD_SLEEP_FLUSH_DISABLE	(1 << 2)
> -- 
> 1.9.1

-- 
Ville Syrjälä
Intel OTC