[Intel-gfx] [PATCH 4/9] drm/i915: Check pixel clock when setting mode for DVO

[Mika Kahola]

It is possible the we request to have a mode that has
higher pixel clock than our HW can support. This patch
checks if requested pixel clock is lower than the one
supported by the HW. The requested mode is discarded
if we cannot support the requested pixel clock.

This patch applies to DVO.

Signed-off-by: Mika Kahola <mika.kahola at intel.com>
---
 drivers/gpu/drm/i915/intel_dvo.c | 21 ++++++++++++++++++++-
 1 file changed, 20 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_dvo.c b/drivers/gpu/drm/i915/intel_dvo.c
index ece5bd7..82cbcea 100644
--- a/drivers/gpu/drm/i915/intel_dvo.c
+++ b/drivers/gpu/drm/i915/intel_dvo.c
@@ -240,16 +240,35 @@ static void intel_dvo_dpms(struct drm_connector *connector, int mode)
 	intel_modeset_check_state(connector->dev);
 }
 
+static int
+intel_dvo_max_pixclk(struct intel_dvo *intel_dvo)
+{
+	struct drm_i915_private *dev_priv = intel_dvo->dev.dev_priv;
+	struct intel_crtc *intel_crtc = to_intel_crtc(intel_dvo->base.base.crtc);
+
+	if (IS_CHERRYVIEW(dev_priv))
+		return  DIV_ROUND_UP(dev_priv->max_cdclk_freq * 100, 95);
+	else if (IS_VALLEYVIEW(dev_priv))
+		return  DIV_ROUND_UP(dev_priv->max_cdclk_freq * 100, 90);
+	else if (IS_BROADWELL(dev_priv) && intel_crtc->config->ips_enabled)
+		return  DIV_ROUND_UP(dev_priv->max_cdclk_freq * 100, 95);
+	else
+		return dev_priv->max_cdclk_freq;
+}
+
 static enum drm_mode_status
 intel_dvo_mode_valid(struct drm_connector *connector,
 		     struct drm_display_mode *mode)
 {
 	struct intel_dvo *intel_dvo = intel_attached_dvo(connector);
+	int max_pixclk = intel_dvo_max_pixclk(intel_dvo);
 
 	if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
 		return MODE_NO_DBLESCAN;
 
-	/* XXX: Validate clock range */
+	/* Validate clock range */
+	if (mode->clock > max_pixclk)
+		return MODE_PANEL;
 
 	if (intel_dvo->panel_fixed_mode) {
 		if (mode->hdisplay > intel_dvo->panel_fixed_mode->hdisplay)
-- 
1.9.1