[Intel-gfx] [PATCH 5/9] drm/i915: Check pixel clock when setting mode for SDVO

[Mika Kahola]

It is possible the we request to have a mode that has
higher pixel clock than our HW can support. This patch
checks if requested pixel clock is lower than the one
supported by the HW. The requested mode is discarded
if we cannot support the requested pixel clock.

This patch applies to SDVO.

Signed-off-by: Mika Kahola <mika.kahola at intel.com>
---
 drivers/gpu/drm/i915/intel_sdvo.c | 21 +++++++++++++++++++++
 1 file changed, 21 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_sdvo.c b/drivers/gpu/drm/i915/intel_sdvo.c
index aa2fd75..34aa657 100644
--- a/drivers/gpu/drm/i915/intel_sdvo.c
+++ b/drivers/gpu/drm/i915/intel_sdvo.c
@@ -1553,11 +1553,32 @@ static void intel_sdvo_dpms(struct drm_connector *connector, int mode)
 	intel_modeset_check_state(connector->dev);
 }
 
+static int
+intel_sdvo_max_pixclk(struct intel_sdvo *intel_sdvo)
+{
+	struct drm_device *dev = intel_sdvo->base.base.dev;
+	struct drm_i915_private *dev_priv = to_i915(dev);
+	struct intel_crtc *intel_crtc = to_intel_crtc(intel_sdvo->base.base.crtc);
+
+	if (IS_CHERRYVIEW(dev))
+		return  DIV_ROUND_UP(dev_priv->max_cdclk_freq * 100, 95);
+	else if (IS_VALLEYVIEW(dev))
+		return  DIV_ROUND_UP(dev_priv->max_cdclk_freq * 100, 90);
+	else if (IS_BROADWELL(dev) && intel_crtc->config->ips_enabled)
+		return  DIV_ROUND_UP(dev_priv->max_cdclk_freq * 100, 95);
+	else
+		return dev_priv->max_cdclk_freq;
+}
+
 static enum drm_mode_status
 intel_sdvo_mode_valid(struct drm_connector *connector,
 		      struct drm_display_mode *mode)
 {
 	struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
+	int max_pixclk = intel_sdvo_max_pixclk(intel_sdvo);
+
+	if (mode->clock > max_pixclk)
+		return MODE_CLOCK_HIGH;
 
 	if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
 		return MODE_NO_DBLESCAN;
-- 
1.9.1