[Intel-gfx] [PATCH 3/7] drm/i915: Don't pass clock to DDI PLL select functions

[Sivakumar Thulasimani]

Reviewed-by: Sivakumar Thulasimani <sivakumar.thulasimani at intel.com>


On 7/6/2015 5:40 PM, ville.syrjala at linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala at linux.intel.com>
>
> All the *_ddi_pll_select() functions get passed the port_clock and pipe
> config as parameters. We only need to pass the pipe config, and the
> functions can dig up the port_clock themselves.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala at linux.intel.com>
> ---
>   drivers/gpu/drm/i915/intel_ddi.c | 20 ++++++++++----------
>   1 file changed, 10 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index 0d3cc98..96fb472 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -1262,9 +1262,10 @@ hsw_ddi_calculate_wrpll(int clock /* in Hz */,
>   static bool
>   hsw_ddi_pll_select(struct intel_crtc *intel_crtc,
>   		   struct intel_crtc_state *crtc_state,
> -		   struct intel_encoder *intel_encoder,
> -		   int clock)
> +		   struct intel_encoder *intel_encoder)
>   {
> +	int clock = crtc_state->port_clock;
> +
>   	if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
>   		struct intel_shared_dpll *pll;
>   		uint32_t val;
> @@ -1543,11 +1544,11 @@ skip_remaining_dividers:
>   static bool
>   skl_ddi_pll_select(struct intel_crtc *intel_crtc,
>   		   struct intel_crtc_state *crtc_state,
> -		   struct intel_encoder *intel_encoder,
> -		   int clock)
> +		   struct intel_encoder *intel_encoder)
>   {
>   	struct intel_shared_dpll *pll;
>   	uint32_t ctrl1, cfgcr1, cfgcr2;
> +	int clock = crtc_state->port_clock;
>   
>   	/*
>   	 * See comment in intel_dpll_hw_state to understand why we always use 0
> @@ -1635,14 +1636,14 @@ static const struct bxt_clk_div bxt_dp_clk_val[] = {
>   static bool
>   bxt_ddi_pll_select(struct intel_crtc *intel_crtc,
>   		   struct intel_crtc_state *crtc_state,
> -		   struct intel_encoder *intel_encoder,
> -		   int clock)
> +		   struct intel_encoder *intel_encoder)
>   {
>   	struct intel_shared_dpll *pll;
>   	struct bxt_clk_div clk_div = {0};
>   	int vco = 0;
>   	uint32_t prop_coef, int_coef, gain_ctl, targ_cnt;
>   	uint32_t lanestagger;
> +	int clock = crtc_state->port_clock;
>   
>   	if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
>   		intel_clock_t best_clock;
> @@ -1770,17 +1771,16 @@ bool intel_ddi_pll_select(struct intel_crtc *intel_crtc,
>   	struct drm_device *dev = intel_crtc->base.dev;
>   	struct intel_encoder *intel_encoder =
>   		intel_ddi_get_crtc_new_encoder(crtc_state);
> -	int clock = crtc_state->port_clock;
>   
>   	if (IS_SKYLAKE(dev))
>   		return skl_ddi_pll_select(intel_crtc, crtc_state,
> -					  intel_encoder, clock);
> +					  intel_encoder);
>   	else if (IS_BROXTON(dev))
>   		return bxt_ddi_pll_select(intel_crtc, crtc_state,
> -					  intel_encoder, clock);
> +					  intel_encoder);
>   	else
>   		return hsw_ddi_pll_select(intel_crtc, crtc_state,
> -					  intel_encoder, clock);
> +					  intel_encoder);
>   }
>   
>   void intel_ddi_set_pipe_settings(struct drm_crtc *crtc)

-- 
regards,
Sivakumar

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